Engineering AI To Be Ethical By Design


I joined Arm because of its amazing people and world-class technology. But while I’m constantly excited by the possibilities of what we can achieve, as Arm’s General Counsel I must also consider the potential harm our designs might cause if they don’t perform in the way we expect, or were put to a use we did not intend. That dilemma comes to the forefront when I think about artificial... » read more

Optimizing Power And Performance For Machine Learning At The Edge


While machine learning (ML) algorithms are popular for running on enterprise Cloud systems for training neural networks, AI/ML chipsets for edge devices are growing at a triple digit rate, according to Tractica “Deep Learning Chipsets” (Figure 1). Edge devices include automobiles, drones, and mobile devices that are all employing AI/ML to provide valuable functionality. Figure 1: Marke... » read more

System-in-Package For Heterogeneous Designs


System integration is increasingly being done using 3D packaging technologies rather than integrating everything onto a huge SoC. One motivation is the ability to not just to split up a design in a single process, but to package die from different processes. Sometimes there are economic reasons. Several presentations at HOT CHIPS had a partition of the design into the processor itself, and a... » read more

Verifying Security In Processor-based SoCs


By Ruud Derwig and Nicole Fern Security in modern systems is of utmost importance. Device manufacturers are including multiple security features and attack protections into both the hardware and software design. For example, the Synopsys DesignWare ARC Processor IP includes many security functions in its SecureShield feature set. End-product system security, however, cannot be guaranteed by ... » read more

Combining Digital Twins And IoT In The Cloud


Engineers are tasked with the continuous improvement of the products, services and systems they design. The trouble is, once a product is out in the field, it’s hard to know how that design is performing — or being used. By coupling digital twin and internet of things (IoT) technology, engineers can get a better idea of a product’s real-world performance. As a reminder, digital twins a... » read more

Opening Up An NVM Evaluation Kit


From toys to smartphones and even mail-order reptiles (a practice which we don’t endorse), unboxing videos are an effective and entertaining way to learn more about a product. According to a recent analysis by Shorr Packaging Corp., toys are the most watched unboxing category, followed closely by smartphones and computers. In addition to providing important product details, an unboxing v... » read more

Verification Pilgrims Show A Historical Case For DFT


The Mayflower Steps, where the Pilgrims are believed to have embarked on their journey to America, are located in the beautiful Barbican area of Plymouth, a small town in the southwest of England. As the lone American working for Moortec, a British company based in Plymouth, I stood and stared at them this past September. Separated by a few yards of distance but 399 years of history I found my... » read more

Virtual System Development Platforms For Safeguarding Complex Microelectronic Systems


Electronic systems are rapidly becoming more complex. This impacts almost all domains in which electronics are used today — especially industrial applications, medical engineering, communications engineering and, of course, automotive applications. What's changed is the addition of huge numbers of sensors and actuators that interact with the environment, the local integration of highly co... » read more

GDDR6 Pushes The Memory Envelope For AI And ADAS


Memory bandwidth is an ever-increasing critical bottleneck for a wide range of use cases and applications. These include artificial intelligence (AI), machine learning (ML), advanced driver-assistance systems (ADAS), as well as 5G wireless and wireline infrastructure. In addition to memory bottlenecks, the above-mentioned use cases and applications are rapidly hitting the real-world limits of t... » read more

Three Steps To Complete Reset Behavior Verification


By Chris Kwok, Priya Viswanathan, and Ping Yeung Reset architectures are notoriously complex and difficult to verify. Today’s SoCs contain highly complex reset distributions and synchronization circuitry. Often, reset trees can be larger than clock trees and have many of the same potential issues. Verifying that a design can be correctly reset under all modes of operation presents signi... » read more

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