category: Low Power-High Performance

category: Auto, Security & Edge AI

Semiconductor Value Chain With A Focus On IP Providers
By Expedera - 16 Jul, 2025 - Comments: 0

By Global Semiconductor Alliance (GSA) The semiconductor industry operates within a complex and rapidly evolving ecosystem driven by continuous innovation. Central to this ecosystem is the semiconductor value chain, which includes several key stages: chip design, wafer fabrication, final assembly, and raw material sourcing. Each stage is crucial to the production and functionality of semicon... » read more

Report: The AI Efficiency Boom
By Arm - 16 Jul, 2025 - Comments: 0

Artificial Intelligence (AI) is undergoing a fundamental transformation. While early AI models were large, compute-heavy, and dependent on cloud processing, a new wave of efficiency-driven innovations is moving AI inference—the generation of model results—to the edge. Smaller models, improved memory and compute performance, and the need for privacy, low latency, and energy efficiency are dr... » read more

Expanding Server Memory Capabilities With Multiplexed Rank DIMM (MRDIMM) Technology
By Rambus - 16 Jul, 2025 - Comments: 0

The scaling of computational power within a single, packaged semiconductor component continues to rise following a Moore’s law type curve enabling new and more capable applications including machine learning (ML), generative artificial intelligence (AI), and training and deployment of large language models (LLM). On-demand lifestyle applications like language translation, direction finding, a... » read more

Research Bits: July 7
By Jesse Allen - 07 Jul, 2025 - Comments: 0

3D NAND PUF Researchers from Seoul National University developed a new hardware security technology based on commercially available 3D NAND flash memory. The approach is an adaptation of physical unclonable functions (PUFs) with the ability to hide a security key under user data when not in use and reveal it only when needed. The same memory space used for storing security keys can be repurpos... » read more

Research Bits: July 1
By Jesse Allen - 01 Jul, 2025 - Comments: 0

Copper-to-copper bonding for GaN integration Researchers from MIT, Georgia Tech, and Air Force Research Laboratory propose a bonding process to integrate gallium nitride (GaN) transistors onto standard silicon CMOS chips. They used the process to create a power amplifier. “We wanted to combine the functionality of GaN with the power of digital chips made of silicon, but without having to ... » read more

Research Bits: June 24
By Jesse Allen - 24 Jun, 2025 - Comments: 0

In-sensor visual processing Researchers from the University of Massachusetts Amherst created silicon-based in-sensor visual processing arrays that can both capture and process visual data in the analog domain to reduce the latency between sensing and identification. The team created two integrated arrays of gate-tunable silicon photodetectors that share bipolar analog output and low-power o... » read more

Research Bits: June 17
By Jesse Allen - 17 Jun, 2025 - Comments: 0

Superlattice castellated FETs Researchers from the University of Bristol and Northrop Grumman Mission Systems discovered a latch-effect in gallium nitride (GaN) that could lead to improved radio frequency device performance, crucial for enabling 6G devices. “We have piloted a device technology, working with collaborators, called superlattice castellated field effect transistors (SLCFETs),... » read more

LLMs On The Edge
By Ed Sperling - 16 Jun, 2025 - Comments: 0

Nearly all the data input for AI so far has been text, but that's about to change. In the future, that input likely will include video, voice, as well as other types of data, causing a massive increase in the amount of data that needs to be modeled and the compute resources necessary to make it all work. This is hard enough in hyperscale data centers, which are sprouting up everywhere to handle... » read more

A Guide To SDC-Based Timing Intent Verification With Questa One
By Siemens EDA - 16 Jun, 2025 - Comments: 0

As semiconductor designs continue to grow in complexity and timing margins become increasingly constrained, achieving predictable timing closure has evolved from a best practice into a critical requirement for first-pass silicon success. At the heart of this process lies the timing constraint file, i.e., the SDC (Synopsys Design Constraints), which defines the intended timing behavior of the de... » read more

The Coming NPU Population Collapse
By Steve Roddy - 12 Jun, 2025 - Comments: 0

At some point in everyone’s teenage years of schooling we were all taught in a nature or biology class about cycles of population surges and then inevitable population collapses. Whether the example was an animal, plant, insect or even bacteria, some external event triggers a rapid surge in the population of a species which leads to overpopulation and competition for resources (food, space, s... » read more

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