Week In Review: Manufacturing, Test


Chipmakers Foxconn is in talks to build a fab in Zhuhai, China, according to a report from Nikkei. The fab, to cost $9 billion, would make chips for Foxconn and outside companies, the report said, which says the company will enter the foundry business. The European Commission has approved funding for 1.75 billion euros ($2 billion) of public investment for projects in the microelectronics... » read more

Week in Review: IoT, Security, Auto


Internet of Things Unmanned aerial vehicles are delivering vaccines to the very remote village of Cook’s Bay, on the island of Erromango, one of 83 volcanic islands in the South Pacific nation of Vanuatu. The drones can go from island to island faster than boats, which often are not a travel option during rough weather. Vanuatu this week began its vaccine deliveries by drones with support fr... » read more

Week In Review: Design, Low Power


Gyrfalcon Technology released a 22nm AI accelerator ASIC chip with embedded MRAM. The Lightspeeur 2802M includes 40MB of memory to support large or multiple AI models, such as image classification and voice identification, within a single chip. Manufactured by TSMC, target applications include IoT endpoints, cloud solutions, and autonomous vehicles. Arm expanded its line of automotive-focuse... » read more

Blog Review: Dec. 19


Cadence's Dave Pursley checks out the state of high-level synthesis and notes that 39% of survey respondents expect to be using it for the majority of designs within three years. In a video, Mentor's Colin Walls digs into how to measure RTOS performance with a focus on interrupt latency. Synopsys' Taylor Armerding chats with Chenxi Wang of Rain Capital to find what the security landscape will... » read more

Week In Review: Manufacturing, Test


Intel Mark Bohr, a senior fellow and director of process architecture and integration at Intel, is retiring, according to the company. Bohr, who will retire at the end of February 2019, held various technology positions during his 41-year career at Intel. Here is a quick bio on Bohr. Others have also recently retired from Intel’s manufacturing unit amid a massive reorganization in the depart... » read more

Week in Review: IoT, Security, Auto


Internet of Things Arm made five 2019 predictions for the Internet of Things. They are: The intelligent home goes mainstream; personalized delivery options; improved health-care service; smart cities seek to improve revenue streams and citizen engagement; and smart buildings use more technology for efficiencies. The company also commissioned a worldwide survey of 2,000 consumers, conducted by ... » read more

Week In Review: Design, Low Power


The MIPI Alliance released MIPI I3C Basic v1.0, a subset of the MIPI I3C sensor interface specification that bundles 20 of the most commonly needed I3C features for developers and other standards organizations. The royalty-free specification includes backward compatibility with I2C, 12.5 MHz multi-drop bus that is over 12 times faster than I2C supports, in-band interrupts to allow slaves to not... » read more

Blog Review: Dec. 12


Mentor's Harry Foster checks out how much time and effort is spent on verification of FPGAs and points to the increasing demand for verification engineers. Cadence's Paul McLellan digs into IC Insights' year-end report to see how some of the top semiconductor companies stack up. Synopsys' Taylor Armerding warns that air gaps, a valuable barrier against cyberattacks, are disappearing from ... » read more

Week In Review: Manufacturing, Test


Fab tools/manufacturing Lam Research has accepted Martin Anstice’s resignation as chief executive and a member of the board. Lam has named Tim Archer as president and chief executive effective immediately. Archer, who served as Lam’s president and chief operating officer, has been named to the board. One analyst provided a comment on the situation at Lam. “In our view, Mr. Archer is very... » read more

Week In Review: Design, Low Power


RISC-V Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in vari... » read more

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