Blog Review: Nov. 11


Mentor's Chris Spear proposes mixing together the compactness of the field macro style with the preciseness of the do methods when writing a UVM transaction class. Cadence's Paul McLellan looks back at the history of EPROM, some of the difficulty with actually erasing it, and the subsequent development of EEPROM. Synopsys' Tuomo Untinen explains three WPA2 authentication vulnerabilities r... » read more

Week In Review: Design, Low Power


Tools Mentor unveiled Tessent Streaming Scan Network software for its Tessent TestKompress software. The new solution includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources for a simplified bottom-up DFT flow. The bus-based scan data distribution architecture enables simultaneous testing of any number of cores and ... » read more

Blog Review: Nov. 4


Arm's Joshua Sowerby points to how to improve machine learning performance on mobile devices by using smart pruning to remove convolution filters from a network, reducing its size, complexity, and memory footprint. Mentor's Neil Johnson checks out how designers can write and verify RTL real-time using formal property checking in the style of test-driven development and why to give it a try. ... » read more

Speeding Up AI With Vector Instructions


A search is underway across the industry to find the best way to speed up machine learning applications, and optimizing hardware for vector instructions is gaining traction as a key element in that effort. Vector instructions are a class of instructions that enable parallel processing of data sets. An entire array of integers or floating point numbers is processed in a single operation, elim... » read more

Week In Review: Design, Low Power


M&A AMD will acquire Xilinx for $35 billion in an all-stock deal. "Joining together with AMD will help accelerate growth in our data center business and enable us to pursue a broader customer base across more markets,” said Victor Peng, Xilinx president and CEO. The deal is expected to close by the end of 2021. The acquisition of the programmable logic giant will leave only a few purepla... » read more

Chinese EDA


If you saw this headline and thought you missed a press release, don't panic. China has not, at this point, announced to the world that it has a suite of EDA tools ready to roll. The rest of the world is content to look at the substandard attempts it have made so far and write them off as not being capable of developing competitive EDA software. But in all likelihood, given the current politica... » read more

A Renaissance For Semiconductors


Major shifts in semiconductors and end markets are driving what some are calling a renaissance in technology, but navigating this new, multi-faceted set of requirements may cause some structural changes for the chip industry as it becomes more difficult for a single company to do everything. For the past decade, the mobile phone industry has been the dominant driver for the semiconductor eco... » read more

Different Requirements For Hyperscale Computing Across Vertical Application Domains


As mentioned in previous posts, one of the key conversations I have with customers a lot these days is how to deal with the balance of storage, compute and connectivity as we enter the era of hyperscale computing. While there are overarching challenges that are “of similar class” across the vertical application domains—consumer, hyperscale computing, mobile, networking, aerospace/defense,... » read more

A Machine Learning-Based Approach To Formality Equivalence Checking


By Avinash Palepu, Namrata Shekhar and Paula Neeley After a long and hard week, it is Friday night and you are ready to relax and unwind with a glass of wine, a sumptuous dinner and a great movie. You turn on Netflix and you expect that it will not only have plenty of pertinent suggestions for you, but also the most appropriate one based on all the previous movies and shows that you have wat... » read more

Solving CSD Verification Challenges


To tackle power consumption and slow execution, modern computational storage devices (CSD) seek to reduce data movement by including a small processing element next to the CSD (figure 1). The data request from the host is executed locally by the processing element, data is locally manipulated, and the result sent back to the host. Much less data is exchanged between storage and host, thus savin... » read more

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