category: System-Level Design

category: Auto, Security & Edge AI

Google Cloud—A View From The Top
By Mike Gianfagna - 27 Jun, 2019 - Comments: 0

I recently had the opportunity to attend a retreat-style event in Napa Valley hosted by the Google Cloud team. Like many such events I’ve attended over the years, the guests were treated to excellent accommodations, fabulous food, a good amount of free time for networking or to partake in activities, relevant and on-point presentations and world-class wine (this is Napa Valley after all). All... » read more

Test Chips Play Larger Role At Advanced Nodes
By Ann Mutschler - 27 Jun, 2019 - Comments: 0

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long b... » read more

DAC 2019 Was About More Than Just Chips
By Jo Windel - 27 Jun, 2019 - Comments: 0

Behind all the noise of the vast array of slot machines, gambling tables and bars and the bright lights of the Las Vegas strip was the large gathering of the annual Design Automation Conference, which was back in the bustling city for the first time in just under 20 years. Following its success in San Francisco last year, and indeed where it will return next July (co-located with the SEMICON... » read more

Verification In The Cloud
By Ed Sperling - 27 Jun, 2019 - Comments: 0

Christen Decoin, senior director of business development at Synopsys, talks with Semiconductor Engineering about what’s changed for EDA in the cloud, why it has taken so long, and what new benefits the cloud will offer. Rules have changed at foundries, and the customer base for designs is evolving. » read more

Meanwhile, 35 Years Later…
By Zibi Zalewski - 27 Jun, 2019 - Comments: 0

At this year’s Design Automation Conference, held on June 3, 4 and 5 in Las Vegas and about 10 miles away from our head office in Las Vegas, Nevada, we celebrated our 35th anniversary with a resounding reaffirmation of our raison d’etre: the provision of verification solutions for some of industry’s most pressing challenges. We had on display a variety of solutions – both hardware ... » read more

Debugging Complex SoCs
By Brian Bailey - 27 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss the debugging of complex SoCs with Randy Fish, vice president of strategic accounts and partnerships for UltraSoC; Larry Melling, product management director for Cadence; Mark Olen, senior product marketing manager for Mentor, a Siemens Business; and Dominik Strasser, vice president of engineering for OneSpin Solutions. What follows are excerpts of ... » read more

Top Considerations For Evaluating The Tech In Tech M&A
By Synopsys - 26 Jun, 2019 - Comments: 0

M&A is high stakes. With thousands of transactions and billions of dollars spent on technology mergers and acquisitions every year, acquirers must protect their investments by conducting due diligence. This white paper discusses: Risks you may encounter in an M&A transaction involving software; How to evaluate these risks using a multifaceted evaluation model; What to look... » read more

Formally Ensuring Equivalence Between C++ And RTL Designs
By Mentor, a Siemens Business - 26 Jun, 2019 - Comments: 0

Moving untimed C++ design descriptions through a High-Level Synthesis (HLS) flow, designers wonder if the generated, timed RTL is functionally equivalent to the original, high-level description. When they make refinements or optimize RTL for power, they naturally are concerned that these changes no longer meet their original specifications. They could create testbenches and run verification at ... » read more

Improving Simulation Throughput Using The Xcelium Parallel Logic Simulator
By Cadence - 26 Jun, 2019 - Comments: 0

Simulators have been around for a long time. First, there were interpreters in the ‘80s and ‘90s, and despite being relatively slow, they were a big step up from fabricating the design and hoping it worked. However, as designs continued to increase in size, the interpreters could not keep up with simulation needs, and innovation was required for simulators to keep pace with new technology. ... » read more

Will Open-Source EDA Work?
By Kevin Fogarty - 26 Jun, 2019 - Comments: 4

Open-source EDA is back on the semiconductor industry's agenda, spurred by growing interest in open-source hardware. But whether the industry embraces the idea with enough enthusiasm to make it successful is not clear yet. One of the key sponsors of this effort is the U.S. Defense Advanced Research Projects Agency (DARPA), which is spearheading a number of programs to lower the cost of chip ... » read more

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