category: System-Level Design

category: Auto, Security & Edge AI

DAC 2019: Day 2
By Brian Bailey - 05 Jun, 2019 - Comments: 0

Day two of DAC started off with a highly anticipated keynote given by Thomas Dolby, musician, producer and innovator. Dolby has always been fascinated with the convergence of music and technology. He started off with a fanfare by balancing a broom on his finger to demonstrate the type of control we have as human beings. He went on to expand the analogy to the hive mind of groups of individuals,... » read more

Training Tomorrow’s Chip Designers
By Ann Mutschler - 05 Jun, 2019 - Comments: 1

With technology advancing rapidly and the growing number of open R&D projects, there is an expanding need for qualified engineers. To make this possible, practical education needs to start much earlier than after graduation. One the best ways the EDA and semiconductor industry has embraced is encouraging engineering students to cooperate with experienced engineers, technologists and indu... » read more

Blog Review: June 5
By Jesse Allen - 05 Jun, 2019 - Comments: 0

Mentor's Neil Johnson argues that coverage closure shouldn't have to be mad scramble in the home stretch of development if designers change their early development mindset. In a video, Cadence's Amol Borkar explains Simultaneous Localization and Mapping, or SLAM, from the creation of a map of an unknown environment and understanding the orientation of a camera in this space. Synopsys' Tay... » read more

DAC 2019: Day 1
By Brian Bailey - 04 Jun, 2019 - Comments: 2

The last time that DAC was in Las Vegas was 2001. Much has changed since then. The first day kicked off with the usual ceremonies and then two short keynotes. A change from previous years is that keynotes are now on the show floor. This is presumably to ensure that once the keynotes are over, everyone sees the vendor booths. During the commencement session, it was also announced that all cof... » read more

CEO Outlook: It Gets Much Harder From Here
By Ed Sperling - 03 Jun, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss what's changing across the semiconductor industry with Wally Rhines, CEO emeritus at Mentor, a Siemens Business; Jack Harding, president and CEO of eSilicon; John Kibarian, president and CEO of PDF Solutions; and John Chong, vice president of product and business development for Kionix. What follows are excerpts of that discussion, which was held in... » read more

Cyber Attacks Against Vehicles On The Rise
By Aileen Ryan - 03 Jun, 2019 - Comments: 0

Who is worried about automotive security and safety? I, for one, most definitely am! I’ve written previously about how tackling this problem makes good business sense. But the more immersed I become in this topic, the more I feel personally concerned about the implications of this, and the snail’s-pace at which the market is responding to it. I’ve just read an Upstream Security repo... » read more

Week In Review: Design, Low Power
By Jesse Allen - 31 May, 2019 - Comments: 0

M&A NXP will acquire Marvell's Wi-Fi Connectivity business in an all-cash, asset transaction valued at $1.76 billion. The deal includes the Wi-Fi and Bluetooth technology portfolios and related assets; the business employs approximately 550 people worldwide. The deal is expected to close by calendar Q1 2020. Tools Cadence unveiled a data center-optimized FPGA-based prototyping system, ... » read more

How Far Can AI Go?
By Ed Sperling - 30 May, 2019 - Comments: 1

AI is everywhere. There are AI/ML chips, and AI is being used to design and manufacture chips. On the AI/ML chip side, large systems companies and startups are striving for orders of magnitude improvements in performance. To achieve that, design teams are adding in everything from CPUs, GPUs, TPUs, DSPs, as well as small FPGAs and eFPGAs. They also are using small memories that can be read i... » read more

Moore Open Source Coming
By Brian Bailey - 30 May, 2019 - Comments: 0

The sunsetting of Moore's Law is creating some interesting ripples throughout the EDA and IP industries. No longer is the low-risk path defined by a migration to the next node. Most companies cannot afford it and don’t need it. Neither can their competitors. Suddenly, they have to do more with less, or at least the same amount. Consider just a few things that are changing today: Stick... » read more

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools
By Chris Giles - 30 May, 2019 - Comments: 0

Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are required to adaptively manage clocks to minimize switching power. Performance and area constraints have led to the abandonment of more conservative practices in favor of more aggressive designs; ... » read more

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