category: System-Level Design

category: Auto, Security & Edge AI

Week In Review: Design, Low Power
By Jesse Allen - 21 Dec, 2018 - Comments: 0

Gyrfalcon Technology released a 22nm AI accelerator ASIC chip with embedded MRAM. The Lightspeeur 2802M includes 40MB of memory to support large or multiple AI models, such as image classification and voice identification, within a single chip. Manufactured by TSMC, target applications include IoT endpoints, cloud solutions, and autonomous vehicles. Arm expanded its line of automotive-focuse... » read more

It’s All About The Data
By Ed Sperling - 20 Dec, 2018 - Comments: 1

The entire tech industry has changed in several fundamental ways over the past year due to the massive growth in data. Individually, those changes are significant. Taken together, those changes will have a massive impact on the chip industry for the foreseeable future. The obvious shift is the infusion of AI (and its subcategories, machine learning and deep learning) into different markets. ... » read more

Top Stories For 2018
By Brian Bailey - 20 Dec, 2018 - Comments: 0

Each year, I look back to see what articles people like to read. The first thing that has amazed me each year at Semiconductor Engineering is that what should be a strong bias towards articles published early in the year never seems to play out. The same is true this year. More than half of the top articles were published after July. The second thing that remains constant is that people love... » read more

Five Rules For Correlating Rule-based And Field Solver Parasitic Extraction Results
By Yousry ElMaghraby - 20 Dec, 2018 - Comments: 0

There comes a time at every foundry and IC design company when it becomes necessary to run a correlation between a rule-based parasitic extraction (PEX) table and a field solver solution. And when that time arrives, there are a few (five, to be precise) details that will help ensure the correlation produces accurate results. But before we get to those, let’s do a quick refresh on PEX techniqu... » read more

Fundamental Shifts In 2018
By Brian Bailey - 20 Dec, 2018 - Comments: 1

What surprised the industry in 2018?  While business has been strong, markets are changing, product categories are shifting and clouds are forming on the horizon. As 2018 comes to a close, most companies are pretty happy with the way everything turned out. Business has been booming, new product categories developing, and profits are meeting or beating market expectations. "2018 was indeed a... » read more

Beyond The RISC-V ISA
By Gajinder Panesar - 20 Dec, 2018 - Comments: 1

For chip architects and designers today, “the ISA” in RISC-V is a small consideration. The concern isn’t even choosing “the core.” Designers today are faced by a “whole system” problem—a problem of systemic complexity. That fact is implicit in the picture that I show people to explain the UltraSoC embedded analytics architecture. It shows a block-level representation of an So... » read more

Verification Throughput Is Set To Increase By Leaps And Bounds In 2019
By Frank Schirrmeister - 20 Dec, 2018 - Comments: 0

In June 2015, I wrote the blog “Towards A Metric To Measure Verification Computing Efficiency” that introduced what we now refer to here at Cadence as the “productivity wheel” for verification payloads—the sequence of “build”, “allocate”, “run” and “debug” that is repeated thousands of times during a project. It was meant to set up the launch of the Palladium Z1 platfo... » read more

Deep Learning Hardware: FPGA vs. GPU
By Farhad Fallahlalehzari - 20 Dec, 2018 - Comments: 0

FPGAs or GPUs, that is the question. Since the popularity of using machine learning algorithms to extract and process the information from raw data, it has been a race between FPGA and GPU vendors to offer a HW platform that runs computationally intensive machine learning algorithms fast and efficiently. As Deep Learning has driven most of the advanced machine learning applications, it is r... » read more

Debug Tops Verification Tasks
By Ann Mutschler - 20 Dec, 2018 - Comments: 0

Verification engineers are spending an increased percentage of their time in debug — 44%, according to a recent survey by the Wilson Research Group. There are a variety or reasons for this, including the fact that some SoCs are composed of hundreds of internally developed and externally purchased IP blocks and subsystems. New system architectures contribute to the mix, some of which are be... » read more

Compute And AI In Next-Generation SSD Designs
By Mike Thompson - 20 Dec, 2018 - Comments: 0

Over the last 40 years digital storage has advanced at an amazing rate. Because it operates out of sight digital storage tends to be taken for granted, but today there is more storage capacity in the devices in our pockets than what existed in mainframe computers 30 years ago. With the rise of artificial intelligence (AI) this trend will continue and the results will be nothing less than astoun... » read more

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