category: System-Level Design

category: Auto, Security & Edge AI

Smarter DFT Infrastructure And Automation Emerge As Keys To Managing DFT Design Scaling
By Ron Press - 21 Dec, 2017 - Comments: 0

By Ron Press and Vidya Neerkundar The reality of DFT for large and complex SoCs has introduced new risk into design schedules. DFT teams end up in the critical path to tape out while waiting for portions of the design to be complete, and there are more DFT integration steps than ever before. The traditional approaches to DFT work on huge designs pose problems of repeatability and reliability... » read more

Bulletproofing Virtual Prototypes
By Malte Doerper - 21 Dec, 2017 - Comments: 0

The big benefits of virtual prototyping methods are that they don’t rely on the availability of RTL or physical hardware. Instead they utilize modes of the future SoC. These models are typically lightweight and optimized for their use case, which is important in regards of simulation speed, modeling and testing effort. Model quality is a key concern, as the virtual prototyping end user accept... » read more

Is Verification Falling Behind?
By Brian Bailey - 21 Dec, 2017 - Comments: 1

Every year that [getkc id="74" comment="Moore's Law"] is in effect means that the [getkc id="10" kc_name="verification"] task gets larger and more complex. At one extreme, verification complexity increases at the square of design complexity, but that assumes that every state in the design is usable and unique. On the other hand, verification has not had the luxury that comes with design reuse b... » read more

What’s Next?
By Mike Gianfagna - 21 Dec, 2017 - Comments: 0

We just concluded two very successful seminars in Tokyo and Shanghai. Samsung Memory presented their HBM2 solutions, Samsung Foundry talked about their advanced 14nm FinFET solutions, ASE Group reviewed their advanced 2.5D packaging solutions, eSilicon presented our ASIC and 2.5D design/implementation and IP solutions, Rambus detailed their high-performance SerDes solutions and Northwest Logic ... » read more

Design Chains Will Drive The Top 5 EDA Trends In 2018
By Frank Schirrmeister - 21 Dec, 2017 - Comments: 0

In my prediction piece last year, I made seven trend predictions. Looking back, I did very well compared to what actually happened. For 2018, I am cutting it down to five trends that will impact EDA, but in my mind a lot of the trends will be driven by the ever-evolving ecosystem of design chains from IP though semiconductor to systems and to OEMs. While HBO’s 'Game of Thrones' comes to a con... » read more

Mixing Interface Protocols
By Ann Mutschler - 21 Dec, 2017 - Comments: 0

Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of assumptions. This is becoming significantly harder as systems become more heterogeneous and as more functions are crammed into those devices. There are more protocols that need to be supported to ... » read more

Using Formal To Solve The World’s Hardest Sudoku
By Saša Stamenković - 21 Dec, 2017 - Comments: 0

It’s no secret that the OneSpin team loves contests. Last year around this time, we set a challenge to engineers everywhere: solve the famous Einstein’s Riddle using a formal tool. After an enthusiastic response, we decided to make the holiday puzzle an annual event, with a different subject area each year. Our engineering team was challenged to come up with a new topic, and my idea, whi... » read more

Using Streamline With Fast Models And Fixed Virtual Platforms
By Ronan Synnott - 21 Dec, 2017 - Comments: 0

In a previous blog I wrote about the Fastline plugin developed for Arm Fast Models, and how it can be used with the Streamline performance analyzer. With the recent release of DS-5 5.28, we have enhanced this experience, including all necessary files within the DS-5 installation, and built-in setup wizards to make it easier to set up and configure. In this blog I will take you through t... » read more

Custom Vs. Non-Custom Design
By Ed Sperling - 21 Dec, 2017 - Comments: 1

Semiconductor Engineering sat down to discuss custom designs with Yong Pang, head of North American operations for [getentity id="22217" e_name="Imec"]; Phil Burr, director of portfolio product management for [getentity id="22186" e_name="Arm's"] embedded and automotive groups; Ambar Sarkar, chief technologist at eInfochips; and John Tinson, vice president of sales at Sondrel. What follows are ... » read more

Partitioning With Ease
By Henry Chan - 21 Dec, 2017 - Comments: 0

Modern ASIC and SoC designs have increased in complexity such that multiple FPGAs of the largest capacity are now required to prototype the entire functionality of the design. As design sizes increase, more and more FPGAs are required. The capacity and pin limitations of FPGAs create constraints for how the ASIC/SoC design can be mapped into the FPGAs. Aldec’s HES-DVM's prototyping mode accou... » read more

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