System Bits: Dec. 20


Removing quasiparticles from superconducting quantum circuits improves lifetime Given that an important prerequisite for the realization of high-performance quantum computers is that the stored data should remain intact for as long as possible, an international team of scientists at European interdisciplinary research institute Forschungszentrum Jülich has succeeded in making further improvem... » read more

The Week In Review: Design


IP eSilicon launched 14nm FinFET and 28nm planar HBM Gen2 Hardened PHY. It supports up to 256Gbytes/sec bandwidth with 8x128b channels at 2Gbps per I/O, and the integrated I/O supports up to 2Gbps DDR operation across a 4mm interposer channel. The PHY was developed on Samsung 14LPP and TSMC 28HPC technologies. Flex Logix designed a high-performance embedded FPGA IP core for TSMC 16FF+ and... » read more

Blog Review: Dec. 14


What are the technology options for 5nm? Cadence's Paul McLellan highlights an IEDM presentation by An Steegen of Imec. Synopsys' Michael Posner suggests we may not have to live with USB Type-C dongles for very long. Mentor's Craig Armenti presents some of the fundamental best practices and guidelines for rigid-flex PCB design. NXP's Joe Byrne digs into the Mirai botnet attack, arguing... » read more

Overcoming The Limits Of Scaling


Semiconductor Engineering sat down to discuss the increasing reliance on architectural choices for improvements in power, performance and area, with [getperson id="11425" comment=" Sundari Mitra"], CEO of [getentity id="22535" comment="NetSpeed Systems"]; Charlie Janac, chairman and CEO of [getentity id="22674" e_name="Arteris"]; [getperson id="11032" comment="Simon Davidmann"] CEO of [getentit... » read more

System Bits: Dec. 13


Data, code sharing standards for computational studies While reporting new research results involves detailed descriptions of methods and materials used in an experiment, when a study uses computers to analyze data, create models or simulate things that can’t be tested in a lab, how can other researchers see what steps were taken or potentially reproduce results? To this end, a new report by... » read more

Formal’s Roadmap


Formal verification has come a long way in the past five years as it focused on narrow tasks within the verification flow. Semiconductor Engineering sat down to discuss that progress, and the future of formal technologies, with [getperson id="11306" comment="Raik Brinkmann"], president and CEO of [getentity id="22395" e_name="OneSpin Solutions"]; Harry Foster, chief verification scientist at [g... » read more

The Week In Review: Design


Standards The latest version of the Bluetooth standard was ratified by the Bluetooth Special Interest Group. Key updates in Bluetooth 5 include four times range, two times speed, and eight times broadcast message capacity, as well as updates that help reduce potential interference with other wireless technologies. Tools Synopsys updated its hierarchical static timing analysis tool for ... » read more

Timing Closure Issues Resurface


Timing closure has resurfaced as a major challenge at 10nm and 7nm due to more features and power modes, increased process variation and other manufacturing-related issues. While timing-related problems are roughly correlated to rising complexity in semiconductors, they tend to generate problems in waves—about once per decade. In SoCs, timing closure problems have spawned entire methodolog... » read more

Blog Review: Dec. 7


Mentor's Harry Foster looks at verification results findings in terms of schedules, number of required spins, and classification of functional bugs, in the latest installment of the Wilson Research Group verification study. Cadence's Paul McLellan provides an overview of the portable stimulus standard currently being worked on at Accellera. Synopsys' Anika Malhotra checks out JESD204B, a ... » read more

System Bits: Dec. 6


Teaching computers to read A multidisciplinary team of UCLA researchers has built a computational model that reflects how humans think and communicate, by designing an algorithm that examined nearly two million posts from popular parenting websites, thereby teaching computers to understand structured narratives within the flow of posts on the internet. Managing large-scale data in this way ... » read more

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