Gaps In The Verification Flow


Semiconductor Engineering sat down to discuss the state of the functional verification flow with Stephen Bailey, director of emerging companies at [getentity id="22017" e_name="Mentor Graphics"]; [getperson id="11079" comment="Anupam Bakshi"], CEO of [getentity id="22168" e_name="Agnisys"]; [getperson id="11124" comment="Mike Bartley"], CEO of [getentity id="22868" e_name="Test and Verification... » read more

System Bits: Oct. 25


Scalable quantum computers In what they say is a significant step towards to the realization of a scalable quantum computer, researchers from the Institute for Quantum Computing (IQC) at the University of Waterloo led the development of a new extensible wiring technique capable of controlling superconducting quantum bits. The quantum socket is a wiring method that uses 3D based on spring-lo... » read more

The Week In Review: Design


Tools Mentor Graphics added RF verification capabilities for wireless applications in the connected sensor and IoT markets to its Tanner design and layout suite. Mentor also integrated its Questa verification tool with the open-source Jenkins Continuous Integration and Source Code Management (CI/SCM) ecosystem. The plugin, a free download, gives Jenkins the ability to utilize regression run ... » read more

Blog Review: Oct. 19


Mentor's Colin Walls provides some tips on writing portable, reusable code. Cadence's Christine Young contends that you should never use 2.5D for characterization at advanced nodes. Synopsys' Eric Huang considers one impractical use of USB heating and the IoT. Applied's Ben Lee predicts a rapid growth in China's power device manufacturing. NXP's Joppe Bos digs into the challenges of... » read more

System Bits: Oct. 18


First quantum computer bridge Quantum computing is closer than we think. For the first time on a single chip, Sandia National Laboratories and Harvard University researchers have shown all the components needed to create a quantum bridge to link quantum computers together by forcefully embedding two silicon atoms in a diamond matrix. Sandia researcher Ryan Camacho pointed out that small qua... » read more

#54DAC: A New Beginning


I’ve been attending DAC as an exhibitor since 1992, and serving on the executive committee since 2012. I am thrilled to serve as General Chair for the 54th iteration of this grand conference. (And no it’s not too early to think about DAC. The call for contributions is open now.) Through the years I have seen some big industry changes, most driven by the increasingly powerful tools and autom... » read more

The Week In Review: Design


M&A Mentor Graphics acquired Galaxy Semiconductor, a provider of test data analysis and defect reduction software ranging from initial characterization of sample devices to automated yield management of large-scale production. The Galway, Ireland company was founded in 1998. Terms of the deal were not disclosed. IP Imagination rolled out a new heterogeneous MIPS CPU with many core/... » read more

Blog Review: Oct. 12


Mentor's Harry Foster digs into verification technology adoption trends for ASIC/IC. Cadence's Tom Anderson looks at the goals of the Portable Stimulus Working Group and how they compare to those of UVM. Synopsys' Eric Huang checks out what's new in the land of USB, Type-C adoption, and cable testing. Ansys' Aveek Sarkar explores the challenges facing 7nm designs and the benefits of ch... » read more

Rethinking Verification For Cars


New tools, approaches, and methodologies are in various stages of development and deployment under the umbrella of functional safety, as more electronics find their way into cars, medical devices and industrial applications. As shown in part one, verification needs to be rethought for these applications. Underneath the umbrella will be ways of doing negative testing, ways of categorizing, an... » read more

Early Power Modeling Using SystemC And TSMC System-PPA


Power consumption is often more important than performance in today’s SoC designs because of battery size and power dissipation limitations. The dilemma is that the most leverage available to optimize power consumption is at the architectural design stage, but there often is not enough information available early enough to make accurate power decisions. On the performance side, SystemC mod... » read more

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