category: System-Level Design

category: Auto, Security & Edge AI

Pain Points At 7nm
By Ed Sperling - 24 Mar, 2016 - Comments: 3

Early work has begun on 7nm. Process technology has progressed to the point where IP and tools are being qualified. There is still a long way to go. But as companies begin engaging with foundries on this process node—[getentity id="22586" comment="TSMC"] is talking publicly about it, but [getentity id="22846" e_name="Intel"], [getentity id="22819" comment="GlobalFoundries"] and [getentity ... » read more

A Formal Transformation
By Brian Bailey - 24 Mar, 2016 - Comments: 0

A very important change is underway in functional verification. In the past, this was an esoteric technology and one that was difficult to deploy. It was relegated to tough problems late in the verification cycle, and it was difficult to justify the ROI unless the technology actually did find some problems. But all of that has changed. Formal verification companies started to use the technology... » read more

Coherency, Cache And Configurability
By Ann Mutschler - 24 Mar, 2016 - Comments: 0

Coherency is gaining traction across a wide spectrum of applications as systems vendors begin leveraging heterogeneous computing to improve performance, minimize power, and simplify software development. Coherency is not a new concept, but making it easier to apply has always been a challenge. This is why it has largely been relegated to CPUs with identical processor cores. But the approach ... » read more

Everything You Wanted to Know About Formal, But Were Too Afraid to Ask
By Dave Kelf - 24 Mar, 2016 - Comments: 0

Formal Verification is one of those EDA technologies that's been used in mainstream development in one or two applications for many years. The true power of the approach only now has started to capture the attention of engineers. Although there are a few reasons for this, perhaps the most significant is formal’s ill-gotten reputation as a mysterious beast too difficult to tame. After worki... » read more

The Making Of A System Architect
By Sundari Mitra - 24 Mar, 2016 - Comments: 0

I mentor young people from the University of Illinois at Urbana-Champaign, where I got my MSEE. When I talk to them, they tell me they’re applying for chip architecture jobs. But when they graduate with their computer science degrees they all get channeled into verification jobs. Why verification jobs rather than architecture jobs? Because they don’t have a feel for the full architecture. T... » read more

Robotics Update From The Playing Field
By Mike Gianfagna - 24 Mar, 2016 - Comments: 0

For those competitive folks out there – which is probably everyone – here is an update on the eSilicon-sponsored robot I spoke of last month. I’m happy to report that our team finished fourth in a field of 24. As of now, they have a good chance of making it to the state-level competition. On top of an already outstanding weekend, our team won the Industrial Safety Award last weekend as we... » read more

An Unsustainable Divide
By Brian Bailey - 24 Mar, 2016 - Comments: 0

One of the great things about attending DVCon, or any other conference for that matter, is the networking. You get to see so many people who are eager to learn, to talk and to share ideas. When this happens, you tend to hear a lot of statements that have to rattle around in your mind for a while before you can start to make sense of them and see if any coherent themes emerge. By themes, I am... » read more

Prototype Like A Pro
By Tom De Schutter - 24 Mar, 2016 - Comments: 0

FPGA-based prototyping has been a key prototyping technique for many years. The steady increase in software content and thus the need to verify and validate the SoC in context of the software has resulted in an equally steady increase in its usage. FPGA-based prototyping or physical prototyping, as it is also called, offers a great way to develop software, verify the hardware in context of that... » read more

Enhanced Electro-Mechanical Collaboration
By Alex Grange - 24 Mar, 2016 - Comments: 0

By Alex Grange and Linda Mazzitelli Integrating electronics into its mechanical environment comes with a number of challenges that boil down to Collision and Connectivity (does the cabinet bang against that capacitor?) and Synchronization (is mechanical designing to the latest PCB design and vice versa?). The culprit to problems that arise usually is the result of poor communications. Mod... » read more

Why Is Semiconductor Schedule Predictability Boring?
By Kurt Shuler - 24 Mar, 2016 - Comments: 0

Why is it not sexy to talk about the manageability of system-on-chip (SoC) projects? As an IP vendor, we are constantly bombarded with questions about how our technology can enhance performance, reduce latency, and lower power consumption. At the same time, reducing cost and time to market for the SoC design conflict with these requirements, even though they rank right up there among the top en... » read more

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