category: System-Level Design

category: Auto, Security & Edge AI

Are Simulation’s Days Numbered?
By Brian Bailey - 24 Mar, 2016 - Comments: 0

In the latest EDAC report, the value of IP surpassed the value of CAE tools for the first time. Verification tools are an important part of establishing confidence in IP blocks and simulation has been the mainstay of that IP verification strategy. But simulation is under increasing pressure, particularly for full-chip and SoC verification, because it has failed to scale. While it still remains ... » read more

How Do Design And Verification Change In The IoT Age?
By Frank Schirrmeister - 24 Mar, 2016 - Comments: 0

Where is the Internet of Things (IoT) on the hype curve? Are expectations too high, or is it really the next big thing? My recent trip to the Design Automation and Test Conference (DATE) in Dresden, Germany, did not give all the answers, but it definitely did shed some light for me on this topic. A very enthusiastic taxi driver took me back 25 years to the Nov. 9, 1989, the time when the Ber... » read more

Why I See C In SCE-MI
By Jacek Majkowski - 24 Mar, 2016 - Comments: 0

The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are, “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”? You a probably reading this during a coffee break, so let’s jump to second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with D... » read more

Accelerating Design-For-Test Pattern Simulation
By Mentor, a Siemens Business - 23 Mar, 2016 - Comments: 0

The Veloce DFT App presents a true “left shift” improvement for a traditional chip design schedule that requires comprehensive gate-level simulations to develop ATPG, BIST, or functional patterns. It enables running complete patterns for DFT verification in a reasonable time to shorten the pattern development cycle. The Veloce DFT App fits seamlessly into the Veloce ecosystem, enabling a ho... » read more

Reducing Verification Risk With Formal-Based Observation Coverage
By OneSpin Solutions - 23 Mar, 2016 - Comments: 0

An effective measure of verification progress, together with guidance towards design areas remaining untested, requires a precise view of the test coverage achieved. To risk signing off the verification process without understanding the quality of testing raises the specter of post-production device bugs. OneSpin Solution’s patented Quantify technology employs Observation Coverage, which eval... » read more

Optimizing DDR Memory Subsystem Efficiency
By Synopsys - 23 Mar, 2016 - Comments: 0

This whitepaper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific SoC application. Starting from a hypothetical Mobile Application Processor design, we will illustrate step-by step how to optimize: Address mapping Clock frequency Quality of Service (QoS) To read more, click here. » read more

The First Fully Configurable Cache-Coherent Interconnect Solution For SoCs
By NetSpeed Systems - 23 Mar, 2016 - Comments: 0

The last few decades have seen a massive growth in the number of CPU cores, computing clusters and other IP blocks in a SoC. This massive growth along with the need for complex chip integration has driven the need for sophisticated interconnects. SoC architects have employed a variety of methods from buses to crossbars to handcrafted NoCs with Lego-like blocks with varying degrees of success. T... » read more

Q&A With FAA DO-254
By Aldec - 23 Mar, 2016 - Comments: 0

Aldec together with FAA DER Randall Fulton conducted a webinar to provide clarifications on some of the most commonly misunderstood objectives and aspects of DO-254. The following is the list of questions that were submitted to Aldec for the webinar. All questions are related to applying DO-254 to FPGAs and PLDs. The answers from Randall Fulton are provided correspondingly. To read more, c... » read more

Tech Talk: ADAS
By Ed Sperling - 23 Mar, 2016 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris, explains what the Advanced Driver Assistance Systems standard is, where the problems are, and why this is becoming so important in automotive semiconductor design. » read more

Blog Review: March 23
By Jesse Allen - 23 Mar, 2016 - Comments: 0

How exactly does a giant fire behave in space? NASA plans to find out, in the latest top five tech picks from Ansys' Justin Nescott. Plus, never scrape ice off your car again and a pangolin-inspired motorcycle helmet. Cadence's Paul McLellan investigates the growing impact of dark silicon as Dennard scaling breaks down and the number of cores in a chip grows. Mentor's Harry Foster present... » read more

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