category: System-Level Design

category: Auto, Security & Edge AI

Blog Review: Sept. 16
By Jesse Allen - 16 Sep, 2015 - Comments: 0

Ansys' Justin Nescott presents five top engineering articles for the week. Being an amateur photography buff, I start salivating at a 250 megapixel camera. Plus, origami and the art of structural engineering and a football-playing robot. Synopsys' Michael Posner provides some shocking information about the buildup of static electricity and the impact it can have on 28nm designs. Increasin... » read more

System Bits: Sept. 15
By Ann Mutschler - 15 Sep, 2015 - Comments: 0

Cache-coherence innovation for thousand-core chips MIT researchers are getting ready to unveil what they say is the first fundamentally new approach to cache coherence in more than three decades. They reminded that in a modern, multicore chip, every processor core has its own small memory cache, where it stores frequently used data. The chip also has a larger, shared cache, which all the cores... » read more

Five Questions: Simon Davidmann
By Ann Mutschler - 14 Sep, 2015 - Comments: 0

Simon Davidmann, president and CEO of Imperas sat down with Semiconductor Engineering to discuss what software engineers want, software development challenges, software reuse, and software quality. SE: What do software engineers want today? Davidmann: We have a narrow view on it because we're coming out of the EDA industry and we're very close to the semiconductors and silicon. The bit th... » read more

The Week In Review: Design/IoT
By Ed Sperling - 11 Sep, 2015 - Comments: 0

Tools Mentor Graphics rolled out a new version of its tool for transferring PCB designs into data for fabrication, assembly and test. The company also announced that its debug environment will support the UPF Low Power Successive Refinement Methodology. Deals Ansys and Cray are claiming the world's record for simulation by scaling 129,000 cores. That's about 4X the previous record.  Ansys... » read more

Blog Review: Sept. 9
By Ed Sperling - 09 Sep, 2015 - Comments: 0

Doulos' John Aynsley explains in a guest blog for Aldec why FPGA designers need to know SystemVerilog and UVM. Might be time to increase the coffee budget. Speaking of verification, Cadence's Frank Schirrmeister notes that his company is joining forces with Mentor Graphics and Breker for a contribution to the Accellera Portable Stimulus Working Group. This is potentially a big deal in veri... » read more

System Bits: Sept. 8
By Ann Mutschler - 08 Sep, 2015 - Comments: 0

Engineering verifies disarmament agreements While it might sound a bit far fetched at first glance, an MIT PhD has developed a tool to identify nuclear weapons. Ruaridh Macdonald, now working on a nuclear weapons verification project in the Laboratory for Nuclear Security and Policy, whereby the linchpin of disarmament agreements is to be able to verify that the signers are following the ru... » read more

The Week In Review: Design/IoT
By Ed Sperling - 04 Sep, 2015 - Comments: 0

IP Synopsys rolled out logic library and embedded memory IP for the Mie Fujitsu 40nm low-power process. The process has 50% lower power consumption compared with previous process technologies. Deals Rambus' Cryptography Research Division won a deal to run the Secure Content Storage Association's cryptographic key management center. The keys are used in SCSA-enabled devices for securing vid... » read more

Blog Review: Sept. 2
By Jesse Allen - 02 Sep, 2015 - Comments: 0

When it comes to cars, manufacturers may be adding too many features too fast, says Mentor's John Day. Up to half of the features may never get used either because they aren't useful or they are too complex. Cadence's Christine Young sat down with Neeti Bhatnagar, a software engineering group director to discuss the challenges and rewards of working in a distributed, cross-functional team, t... » read more

System Bits: Sept.1
By Ann Mutschler - 01 Sep, 2015 - Comments: 0

The quantum description of nature In quantum mechanics, the underlying physical rules that govern the fundamental behavior of matter and light at the atomic scale state that nothing can quite be completely at rest, but now for the first time, a team of researchers from Caltech, McGill University, and the Max Planck Institute for the Science of Light has found a way to observe—and control—t... » read more

Making Hardware Design More Agile
By Ed Sperling - 31 Aug, 2015 - Comments: 1

Semiconductor engineering sat down to whether changes are needed in hardware design methodology, with Philip Gutierrez, ASIC/FPGA design manager in [getentity id="22306" comment="IBM"]'s FlashSystems Storage Group; Dennis Brophy, director of strategic business development at [getentity id="22017" e_name="Mentor Graphics"]; Frank Schirrmeister, group director for product marketing of the System ... » read more

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