category: System-Level Design

category: Auto, Security & Edge AI

System Bits: April 15
By Ann Mutschler - 15 Apr, 2014 - Comments: 0

Making game play more engaging Engineers at Stanford University have developed what could be the next big thing in interactive gaming: handheld game controllers that measure the player's physiology and alter the game play to make it more engaging. The prototype controller was born from research conducted in the lab of Gregory Kovacs, a professor of electrical engineering at Stanford, in collab... » read more

The Week In Review: Design
By Ann Mutschler - 11 Apr, 2014 - Comments: 0

Tools Mentor Graphics announced its Enterprise Verification Platform (EVP) that pulls together the company’s Questa verification technologies with Veloce OS3 global emulation resourcing technology, and the Visualizer debug technology into what it says is a globally accessible, high-performance datacenter resource. The system is aimed at global resource management and supports project teams a... » read more

Blog Review: April 9
By Ed Sperling - 09 Apr, 2014 - Comments: 0

Mentor’s Colin Walls discovered an interesting video of the software programming learning process—a teacher responding literally to commands from his students on how to make a jam sandwich. It’s harder than it looks. Cadence’s Brian Fuller captures a speech by his colleague, Sanjiv Taneja, about the need for a comprehensive verification approach and smart IP reuse. The overriding th... » read more

System Bits: April 8
By Ann Mutschler - 08 Apr, 2014 - Comments: 0

Quantum photon properties revealed in plasmon particle For years, researchers have been interested in developing quantum computers—the theoretical next generation of technology that will outperform conventional computers that involves storing information in qubits rather than in bits used by computers today. One approach for computing with qubits relies on the creation of two single photons ... » read more

The Week In Review: Design
By Ed Sperling - 04 Apr, 2014 - Comments: 0

Tools Mentor Graphics rolled out a new platform for verification of unknown voltage levels (Xs) at the register transfer and gate levels, fusing together simulation and formal verification under one umbrella. The company says the approach will limit bugs and wasted effort caused by X-optimism and pessimism. Jasper Design Automation unveiled a new tool to verify the sequential functional equ... » read more

Inside SI2’s OpenPCell Workshop
By Steve Schulz - 03 Apr, 2014 - Comments: 1

In the last Standards and Beyond blog, we provided background on the Open Process Specification, including where pcells fit into the overall picture, and gave an invitation to the OpenPCell workshop being hosted by the Silicon Integration Initiative (Si2). The ensuing workshop, held on Jan. 29, was well attended with more than 35 companies represented across the globe. It was a gathering of man... » read more

Blog Review: April 2
By Ed Sperling - 02 Apr, 2014 - Comments: 0

Mentor’s Nazita Saye compares roadway roundabouts to networked systems. One roundabout works fine, but add in a bunch of them and you have a massive traffic jam. How many roundabouts are in your design? Cadence’s Richard Goering interviews Stan Kroliskoski, chair of the IEEE Design Automation Standards Committee, about four working groups on EDA standards and what’s ahead. Speaking ... » read more

EDA Sales Up Again
By Ed Sperling - 01 Apr, 2014 - Comments: 0

EDA continued to post strong growth, setting records as an industry and proving the resilience of the tools industry, which has been showing positive numbers for 16 consecutive quarters. Revenue for Q4 of 2013 were $1.881 billion, up from $1.779 billion in the same period in 2012, according to numbers provided by the EDA Consortium. For the year, revenue hit $6.932 billion, up 6.1% from annu... » read more

System Bits: April 1
By Ann Mutschler - 01 Apr, 2014 - Comments: 0

“Lock-free” vs. “wait-free” parallel algorithms Since computer chips have stopped getting faster, regular performance improvements are now the result of chipmakers’ adding more cores to their chips, rather than increasing their clock speed. And in theory, doubling the number of cores doubles the chip’s efficiency, but splitting up computations so that they run efficiently in parall... » read more

Big Shift In SoC Verification
By Ed Sperling - 31 Mar, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss software-driven verification with Ken Knowlson, principal engineer at Intel; Mark Olen, product manager for the Design Verification Technology Division of Mentor Graphics; Steve Chappell, senior manager for CAE technology and verification at Synopsys; Frank Schirrmeister, group director for product marketing of the System Development Suite at Cadenc... » read more

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