category: System-Level Design

category: Auto, Security & Edge AI

What Should I Build?
By Tom De Schutter - 24 Apr, 2014 - Comments: 0

The question in the title has been one of the most asked questions by my son lately. Or as my wife says, his brain is 90% focused on Minecraft and 10% on everything else. For those not familiar with Minecraft, it is a lego-like computer game or as the Minecraft website reads: “Minecraft is a game about breaking and placing blocks.” It has literally captured the imagination of my son and ... » read more

Rethinking SoC Verification
By Various Writers - 23 Apr, 2014 - Comments: 1

The introduction of the iPhone in 2007 represented a fundamental shift in electronic system design: moving advanced processing power off of the desktop and into the hands of users everywhere, always. This shift has led to a revolution in mobile—the expansion into the Internet-of-Things, with wearables, connected automobiles and homes. This revolution is causing profound technology challeng... » read more

Hierarchical Timing Analysis: Pros, Cons, And A New Approach
By Various Writers - 23 Apr, 2014 - Comments: 0

As digital semiconductor designs continue to grow larger, designers are looking to hierarchical methodologies to help alleviate huge runtimes. This approach allows designers to select and time certain blocks of logic, generating results more quickly and with fewer memory resources. However, these benefits come at the cost of accuracy. This paper covers the pros and cons of different hierarchica... » read more

How To Improve The Profitability Of Fabless Semiconductor Companies
By Various Writers - 23 Apr, 2014 - Comments: 0

Semiconductor industry gross margins are under pressure. The average gross margin of the industry in Q4 2013 was 53 percent, which was a quarter-over-quarter decline of over 100 basis points (bps), and a continued decline of over 300 bps from the high water mark in Q3 2010 of 56 percent. This white paper explores several effective strategies available to meet the challenges of managing the c... » read more

Localized, System-Level Protocol Checks And Coverage Closure
By Various Writers - 23 Apr, 2014 - Comments: 0

Broadcom recently developed a unified, scalable, verification methodology based on the Veloce emulation platform. In order to test this new environment, they ran a test case, which proved that they can take assertions, compile them into Veloce, and verify that they fire accurately. In so doing, they were able to provide proof of concept for their primary goal: the creation of an internal flow t... » read more

Blog Review: April 23
By Ed Sperling - 23 Apr, 2014 - Comments: 0

Mentor’s John Day looks backward through a smart rearview mirror from Nissan. No glare, even at night or at sunset, and a wider field of vision. You have to wonder why this technology took so long. Synopsys’ Karen Bartleson wonders when the IoT will actually arrive, given the delay in durable goods, a concern over security and the effects of government regulation. Answer: When we stop ta... » read more

System Bits: April 22
By Ann Mutschler - 22 Apr, 2014 - Comments: 0

To mimic human cognition In the field of neuromorphic engineering, researchers study computing techniques that could someday mimic human cognition and to this end, electrical engineers at the Georgia Institute of Technology recently published a "roadmap" that details innovative analog-based techniques that could make it possible to build a practical neuromorphic computer. [caption id="attac... » read more

Cadence Gobbles Up Jasper
By Brian Bailey - 21 Apr, 2014 - Comments: 4

2012 was the year that everyone remembers Synopsys going on an acquisition binge, but 2014 will go down as the year that Cadence Design Systems decided that EDA was worth investing in. Rather than placing investment bets outside of its core competence, Cadence bought Forte in February and now adds Jasper Design Automation to its fold. Jasper started life as Tempus Fugit in 1999 and became Ja... » read more

The Week In Review: Design
By Ed Sperling - 18 Apr, 2014 - Comments: 0

Certifications TSMC certified Mentor Graphics’ DFM, place and route and custom IC tools, as well as its SPICE simulator, for the 16nm finFET process.  The foundry also certified Cadence’s digital and custom/analog tools for that process, including physical verification, QRC extraction, timing sign off and its power integrity solution. And it certified Synopsys’ digital and custom soluti... » read more

Blog Review: April 16
By Ed Sperling - 16 Apr, 2014 - Comments: 0

Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

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