2014 Accellera Standards Are Built on Powerful Shoulders


By Adam Sherer Looking out at the fresh snow coating the landscape here in Buffalo, it’s tempting to look toward 2014 and focus only on the fresh and new. However, if I’ve learned anything about this city from the day I arrived here as a freshman EE in 1984, it’s that you don’t bury your foundation. Instead, you recognize it as your greatest strength, the powerful shoulders upon whic... » read more

A Perspective On Open Process Specification


It is the job of the Process Design Kit (PDK) engineers to deliver a high-quality PDK that properly represents the process requirements and constraints and supports the design flows used by their customers. The PDK engineer takes multiple inputs describing the process and the devices and circuitry in the process and generates the output in the form of OpenAccess technology libraries (techDB), d... » read more

Tech Talk: Changes In Verification


Roger Hughes, director of strategic accounts at Real Intent, talks about what's changing in verification as design complexity increases and where engineers typically make mistakes. [youtube vid=0SE97LvCilo] » read more

The Week In Review: System-Level Design


India's reliance on technology has created a huge demand for software in the country. IDC expects the market for enterprise software in India to grow 19%, and the market for collaborative applications to grow 13.5%. Growth is continuing across all business markets, turning India into a huge consumer of software rather than just a creator. The enterprise software market in India is dominated by ... » read more

Defining The Next Standard Cell


Synopsys, Intel and IBM all contributed technology to Si2 to create a standard version of parameterized cells, or PCells, for mixed-signal designs. The move is an attempt to smooth out design incompatibilities using Synopsys and Cadence technology. Cadence is the clear market leader in this space. But as more technology is developed using different vendors'  tools for integration in complex... » read more

Blog Review: Jan. 22


Mentor’s Anil Khanna believes Nest’s approach should be incorporated into the entire power grid. The ramifications of that are interesting to ponder. Speaking of Nest, Cadence’s Brian Fuller looks at the implications of the $3.2 billion acquisition of the company by Google. Will Google get it right? Maybe. Synopsys’ Richard Solomon has come up with a new definition for New Year’... » read more

System Bits: Jan. 21


Metamaterial modeling Metamaterials -- artificial materials engineered to have properties that are not normally found in nature and being explored in a number of technologies such as perfect lenses, antennas and terahertz devices – are becoming more important to model. Modeling them is a difficult task considering their unconventional nature and delicate properties but researchers from Ecole... » read more

Experts At The Table: What’s Next?


Semiconductor Engineering sat down with Sumit DasGupta, Si2; Simon Bloch, Samsung; Jim Hogan, long-time industry venture capitalist; Mike Gianfagna, vice president of marketing at eSilicon (VP of corporate marketing at Atrenta when this roundtable was held). What follows are excerpts of that discussion. SE: What’s going to really drive interest in low-power technology? Hogan: The world ... » read more

Establishing The Calendar


Back in the dawn of time, when man settled down, stopped being a nomad and wanted to plant crops, it became important to be able to measure time. When was the right time to plant crops and to harvest? When could the rains be expected to come? When would the first frost come? It was no longer good enough to trust doing the happy rain dance or to pray to some gods. It was better to know and under... » read more

Week In Review: System-Level Design


Cadence rolled out a new version of its functional verification platform, greatly improving performance and updating it to deal with the big increases in third-party and re-used IP in designs. For IP and block verification, the company said it increased formal analysis performance by up to 20% and simulation by up to 10 times. The debugger also reduces the database size by 10 times and the time... » read more

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