category: System-Level Design

category: Auto, Security & Edge AI

The Week In Review: System-Level Design
By Ed Sperling - 27 Nov, 2013 - Comments: 0

Synopsys won a deal with Germany’s Hyperstone, which will use Synopsys verification tools for SoCs in industrial, automotive and medical applications. As SoCs used in industrial and “safety-critical” markets grow in complexity and move to more advanced process nodes, more advanced tools also are necessary. Si2 uncorked a new release of its OpenAccess scripting interface—oaScript Exte... » read more

Blog Review: Nov. 27
By Ed Sperling - 27 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory is looking at real-world experiments to figure out which EDA software is better. Make sure to check out his stats. Cadence’s Brian Fuller interviews two Samsung engineers in a video about the image technology in smart phone cameras and just how far it’s progressed. Hint: Don’t forget to charge your phone on your next vacation. Mentor’s Colin Walls points ... » read more

System Bits Nov 26
By Brian Bailey - 26 Nov, 2013 - Comments: 0

Scaling The Quantum Slopes Like any task, there are easy and hard ways to control atoms and molecules as quantum systems, which are driven by tailored radiation fields. More efficient methods for manipulating quantum systems could help scientists realize the next generation of technology by harnessing atoms and molecules to create small but incredibly powerful devices, such as molecular electr... » read more

Big Changes Rock Global Smartphone Market
By Jeff Chappell - 25 Nov, 2013 - Comments: 0

BANGKOK — One of the many draws for Western travelers here in Thailand and throughout much of Asia, including China, is the availability of cheap consumer electronics. Unfortunately many of these electronic goods — little-known off-brands mimicking better-known counterparts, or white-label devices being passed off as name-brand products to unsuspecting consumers — typically are technologi... » read more

The Week In Review: System-Level Design
By Ed Sperling - 22 Nov, 2013 - Comments: 0

Synopsys rolled out new non-volatile memory IP that cuts power by 90% and reduces area in half. The company said it accomplished this feat with a single-bit read capability, which can drop read operation down to 0.9 volts and peak current to less than 10 microamps during erase and programming. The target of the ultra-low power IP is RFID and near-field computing ICs. Mentor Graphics posted p... » read more

Is There Light At The End Of Moore’s Tunnel
By Brian Bailey - 22 Nov, 2013 - Comments: 2

Electrons are slow, clumsy and quite easily distracted. They’re slow because it now takes a signal longer to cross a chip than the period of the clock signal. They often don’t travel in straight lines as they collide with other atoms. And electromagnetic interference between adjacent signals can mess with the information they are transferring. On the other hand, light has none of these p... » read more

Sometime More Is More And Less…
By Neil Hand - 22 Nov, 2013 - Comments: 0

Anyone who has been reading this blog has already figured out that as an ex-system designer, I am a fan of intelligent IP subsystems, and in a couple of my previous posts I already talked about how they make design easier by distributing the overall complexity. The other day however, I found myself trying to describe to a non-semiconductor person why this move is good and what benefits it de... » read more

Even Standard IP Isn’t Always Standard
By Ed Sperling - 21 Nov, 2013 - Comments: 0

Time to market and rising complexity are forcing the use of more third-party IP as well as increasing reuse of internally developed IP. But as more IP is added into SoCs, chipmakers are discovering some interesting things: Not all IP works together as planned, even when it’s well characterized. As with cars, performance and mileage vary greatly depending upon who’s driving—and who’s... » read more

Improving Design Reliability By Avoiding Electrical Overstress
By Various Writers - 21 Nov, 2013 - Comments: 0

Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage ... » read more

Do Students Need More Formal Education?
By Brian Bailey - 21 Nov, 2013 - Comments: 0

A few weeks ago, some of the top researchers and practitioners in the area of formal methods converged on Portland, Oregon. The event was the annual Formal Methods in Computer-Aided Design (FMCAD) conference and Semiconductor Engineering attended the panel titled “Teaching Formal Methods: Needs, Challenges, Experiences, and Opportunities.” Panelists included: Jason Baumgartner, formal verif... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy