category: System-Level Design

category: Auto, Security & Edge AI

Experts At The Table: Debug
By Ed Sperling - 26 Sep, 2013 - Comments: 0

By Ed Sperling Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation. SE: What are the big issues with debug? ... » read more

More Test Needed For Integrated IP
By Ann Mutschler - 26 Sep, 2013 - Comments: 0

By Ann Steffora Mutschler As the use and reuse of design IPs and cores has reached approximately 70% of the content of an SoC, the need for both pre- and post-silicon test has increased. On the pre-silicon side, test comes in the form of verification IP. Driving the addition of more strenuous test approaches on this side is a combination of forces that impact design, noted Tom Hackett, prod... » read more

What Type of Insurance Do You Have?
By Tom De Schutter - 25 Sep, 2013 - Comments: 0

With the software development effort now accounting for roughly half of the overall SoC development cost, any delay on the software availability side can have a big impact on the SoC availability. As one engineer of a major semiconductor vendor expressed to me: “The SoC hardware is typically only available a couple of weeks before we want to announce and demonstrate it at a major show like CE... » read more

NoC Straight Talk
By Frank Ferro - 25 Sep, 2013 - Comments: 0

Increased interest in on-chip network IP is without a doubt directly correlated to the increase in SoC complexity and performance over the past few years. Some SoC design managers even have gone so far as to say that the success of their SoC program is directly related to their ability to implement an on-chip communications network. Underestimating the importance of the on-chip network has caus... » read more

Blog Review: Sept. 25
By Ed Sperling - 25 Sep, 2013 - Comments: 0

By Ed Sperling Mentor’s Michael Ford has replaced his dingy bathroom lights with LEDs, and now he literally can see all the stuff that needs to be fixed. Sound familiar? Synopsys’ Mick Posner pulls out the old bread and drink mnemonic for which water glass is yours at a crowded table. But what do you do when someone else gets it wrong? “Excuse me, that’s my FPGA prototyping board.�... » read more

System Bits: Sept. 24
By Ann Mutschler - 24 Sep, 2013 - Comments: 0

Printing nanostructures with self-assembling material A multi-institutional team of engineers from the University of Illinois at Urbana-Champaign, the University of Chicago and Hanyang University in Korea has developed a new approach to the fabrication of nanostructures for the semiconductor and magnetic storage industries. The approach combines top-down advanced ink-jet printing technology... » read more

The Week In Review: Sept. 20
By Ed Sperling - 20 Sep, 2013 - Comments: 0

By Ed Sperling It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies. It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, inclu... » read more

Blog Review: Sept. 18
By Ed Sperling - 18 Sep, 2013 - Comments: 0

By Ed Sperling It’s amazing how irresistible an engineer suddenly becomes when he has an FPGA prototyping board in his hands. Check out the photo of Synopsys’ Mick Posner in Taiwan. Cadence’s Brian Fuller digs into semiconductor startups, why there’s been such a lull, and how new startups are changing. Mentor’s John Day picks out a new product category from TI—inductance to... » read more

System Bits: Sept. 17
By Ann Mutschler - 17 Sep, 2013 - Comments: 0

Multicore memory management According to MIT researchers, it may be time to let software rather than hardware manage high-speed on-chip memory caches. Traditionally, managing the caches has required fairly simple algorithms that can be hard-wired into the chips but as multiple cores in SoCs proliferate, cache management becomes much more difficult. As such, MIT’s Department of Electric... » read more

The Week In Review: Sept. 13
By Ed Sperling - 13 Sep, 2013 - Comments: 0

By Ed Sperling Cadence unveiled its next-generation emulation platform, greatly boosting the speed by up to 60x for embedded OS verification and by up to 10x for hardware/software verification. Overall, Cadence says the platform doubles verification productivity with a capacity of up to 2.3 billion gates. Cadence also reported that its mixed-signal LP flow allowed Silicon Labs to cut its MCU p... » read more

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