category: System-Level Design

category: Auto, Security & Edge AI

Getting Ahead Of Yourself
By Jon McDonald - 24 May, 2012 - Comments: 0

By Jon McDonald Recently we've been doing some minor remodeling in our house—nothing requiring major contractors. It’s mostly smaller things that unfortunately require a significant amount of personal involvement. Over the course of the past few weeks we've had a number of "projects" that we've started, then had to undo what was done because we were interfering with another area of work. M... » read more

UVM Do’s And Don’ts For Effective Verification
By Various Writers - 24 May, 2012 - Comments: 0

With more than a year of production use, the Accellera Systems Initiative UVM is now clearly the methodology of choice for verification. The rush to adopt UVM has both matured the BCL quickly, producing UVM 1.1 and 1.1a bug-fix versions, as well as created a wealth of institutional know-how. Of course, the challenge with know-how is that it tends to be distributed among all the members of the c... » read more

Audio Subsystems For Efficient SoC Integration
By Various Writers - 24 May, 2012 - Comments: 0

Implementing advanced audio functionality in a system-on-chip (SoC) involves integrating a range of hardware and software components, including an audio processor, audio peripherals, software drivers, and audio processing software. In this white paper, we discuss the requirements for audio solutions for processing of high-definition (HD) multi-channel audio and detail the challenges involved in... » read more

NoC Power Benefits
By Various Writers - 24 May, 2012 - Comments: 0

The system-on-chip (SoC) interconnect spans the entire floorplan of a chip and consumes a significant portion of the power. The interconnects of today’s SoCs are a distributed architecture of switches, buffers, firewalls, register slices, and clock and power domain crossings. One approach is to implement these units modularly with a simple, universal transport protocol between all units... » read more

Understanding Via Effects
By Various Writers - 24 May, 2012 - Comments: 0

As the demand for fast computation and information transmission has increased dramatically in recent years, many designs have boards with signals operating in the multiple-Gbps range. Advanced memory designs are targeting over 10 Gbps data rates while the SERDES standard is moving toward 25-28 Gbps. With the signal speed changes come the new challenges of solving design issues never seen before... » read more

Tech Talk: Coherency’s Next Frontiers
By Ed Sperling - 23 May, 2012 - Comments: 0

Laurent Moll, CTO of Arteris, talks about new types of coherency and why it will be such a big challenge. [youtube vid=lufY9yDLjwE] » read more

Tech Talk: Cloud-Scale SoCs
By Ed Sperling - 23 May, 2012 - Comments: 0

Sonics CTO Drew Wingard talks about what's changing in SoC design as performance ramps up on mobile devices and power is ratcheted down to save battery life. [youtube vid=cdzhFCsLyyI] » read more

Endless Abstractions?
By Frank Schirrmeister - 22 May, 2012 - Comments: 1

By Frank SchirrmeisterHaving started my own career doing full custom layout, then moving though gates and RTL to transactions and embedded software, I always was a little bit concerned whether the industry would eventually run out of abstraction levels for me to adopt further upwards. It looks like there is plenty of head room.Last week I was in Munich attending the CDNLive! EMEA event. I was h... » read more

Experts At The Table: Hardware-Software Co-Design
By Ed Sperling - 11 May, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, direct... » read more

Experts At The Table: Hardware-Software Co-Design
By Ed Sperling - 04 May, 2012 - Comments: 0

By Ed Sperling System-Level Design sat down to discuss hardware-software co-design with Frank Schirrmeister, group marketing director for Cadence’s System and Software Realization Group; Shabtay Matalon, ESL market development manager at Mentor Graphics; Kurt Shuler, vice president of marketing at Arteris; Narendra Konda, director of hardware engineering at Nvdia; and Jack Greenbaum, directo... » read more

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