category: System-Level Design

category: Auto, Security & Edge AI

Beyond 22nm
By Ed Sperling - 15 Dec, 2010 - Comments: 0

Gary Patton, VP at IBM's semiconductor R&D Center, talks with System-Level Design about the challenges of developing chips all the way down to 15nm. [youtube vid=2wTj3EvRIRw]   » read more

The Ever-Growing System Challenge
By Jon McDonald - 10 Dec, 2010 - Comments: 0

It used to be easy to define a system. It was an ASIC, an ASSP or even an SoC. Increasingly, however, that definition isn’t nearly broad enough. With power issues now spreading across an entire device and software being used to manage everything from embedded applications to board-level functionality, the system is now much bigger than a single chip or even a system in package. It now enc... » read more

The Rising Stake In Software Tools
By Ed Sperling - 03 Dec, 2010 - Comments: 0

By Ed Sperling The growing importance of software and off-the-shelf IP in semiconductor design is beginning to change the dynamics of the entire EDA tools business, setting off a string of acquisitions as the largest players realign themselves to take advantage of this shift. The most recent example: Mentor Graphics’ acquisition this week of CodeSourcery, a GNU-based Linux toolchain and s... » read more

Standards Update
By Ann Mutschler - 18 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler In the sometimes-murky waters of system-level modeling standards where real-world adoption can be difficult to track, work is progressing to help hardware and software engineers realize the promise of true hardware-software codesign. The three main standards efforts related to modeling at the system level are OSCI’s TLM-2.0, OCP-IP’s OCP and Open Modeling TAB a... » read more

Reducing Bottlenecks
By Ann Mutschler - 18 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler For the first time ever, China recently earned fastest supercomputer bragging rights with its Tianhe-1A supercomputer, which can perform 2.57 quadrillion computing operations per second. The machine has been successfully used to survey mines, forecast weather and design high-end machinery. While it has caused concern, it is important to note that the Tianhe-1A use... » read more

Building Up In 3D
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Stacked die are expected to begin showing up in volume in late 2012 and in 2013, turning what has been a science experiment into a mainstream way of designing and manufacturing SoCs. This magnitude of this shift cannot be overstated, and clearly all of the pieces are not in place to make it all happen immediately. There also are significant technology challenges to overcome, ... » read more

Verifying At The System Level
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Verification has always been the problem child of SoC design. It requires the most engineering resources, the largest block of time and the biggest budget in the design process. And at each new process node the problem gets bigger, in part because there is more stuff on each die—transistors, memory, interconnects, I/O, functionality—and in part because chipmakers are being c... » read more

Changes Ahead
By Ed Sperling - 18 Nov, 2010 - Comments: 0

With 3D stacked die looking increasingly promising, the question for much of the industry is exactly when this will happen, how it will happen, and what it will mean to the design process. To a large extent, in an attempt to buffer the risk, much of the fabless industry has been heading toward FPGA prototypes. It is uncertain whether that trend will continue at the same pace as 3D processes ... » read more

Just Kidding
By Jack Harding - 18 Nov, 2010 - Comments: 0

By Jack Harding I can remember back to 1995 and the first time I heard Joe Costello at Cadence speak publicly about the “disaggregation of the supply chain.” Disaggregation? Was that even a word in Webster’s Dictionary? It didn’t matter because, like many other concepts championed by Joe, it was the word every journalist and analyst in the semiconductor space was using to describe t... » read more

Behind The Standards
By Kurt Shuler - 18 Nov, 2010 - Comments: 0

By Kurt Shuler As engineers, we view transaction protocols as simply a language to be able to communicate information from one block of system-on-chip (SoC) IP to another block. However, if you look at transaction protocols from an economics framework you see there's much more to it. With the past interconnect fabrics dominated by crossbars and hierarchal busses, the choice of the IP transacti... » read more

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