category: System-Level Design

category: Auto, Security & Edge AI

Boost For Verification Methodologies
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Synopsys introduced enhancements to its Verification Methodology Manual and Cadence began detailing new enhancements in its Open Verification Methodology. Both programs are in beta, yet they offer steps forward toward easing one of the biggest problem areas in chip development. With verification still consuming 70% or more of the non-recurring engineering costs of semicondu... » read more

Lots Of Work To Be Done
By Ed Sperling - 25 Jul, 2009 - Comments: 0

Many design engineers have had a long time to think about what’s changed in the design world. Some of them are still looking for jobs, frustrated by the remarkably slow pickup in the job market—particularly in the United States and Europe. But as Magma CEO Rajeev Madhavan noted last year, coming out of the downturn things may not look the same as when we went into the downturn. It’s ... » read more

DAC Attack
By Ed Sperling - 24 Jul, 2009 - Comments: 0

Designing chips has always attracted the best and the brightest minds. The sheer complexity of creating submicron technology creates challenges in mathematics, physics and science, and if intellectual stimulation ever wanes there’s always the problems associated with the next process node. Moore’s Law sees to it that new and interesting challenges always have to be met. But it does not... » read more

Pain Points In System-Level Design
By Ed Sperling - 24 Jul, 2009 - Comments: 0

Synopsys CEO Aart de Geus digs into what's changing in design, what's driving it, and what the future will bring. [youtube vid=a1ozKqlqVHs] » read more

ESL…Is It What You Want Or What You Need?
By Jon McDonald - 25 Jun, 2009 - Comments: 0

Last week I was sitting in a meeting having an extended discussion on what information and benefits could be derived from an ESL transaction model of a system.  It reminded me of the words of those immortal philosophers, The Rolling Stones, “You can’t always get what you want, but if you try sometimes you just might find, you get what you need”.  I believe this is a philosophy that ne... » read more

Making Quality A Top Priority in Next-Generation Designs
By Cheryl Ajluni - 25 Jun, 2009 - Comments: 0

By Cheryl Ajluni With system design such a complicated task these days, it is increasingly likely that designers will inadvertently overlook some details of the design process, or worse yet, simply not have the time to address them adequately. Time is readily spent focusing on things like performance, area, timing, and power, but what about something a bit more esoteric in nature—namely, qu... » read more

Custom IC Design: They Call This Progress?
By Ed Sperling - 25 Jun, 2009 - Comments: 0

By Ed Sperling For decades, analog and digital engineers have lived in completely separate worlds. The lines are blurring between those worlds, though, in complex SoCs. So far, the transition has been difficult, and most engineers predict it will get worse at future process nodes. The basic problem is that each world has functioned independently of the other from the start. They use different... » read more

Where The Jobs Are
By Ed Sperling - 19 Jun, 2009 - Comments: 0

The job market for design and verification engineers seems to be exploding. In the past week, listings have been flooding onto jobs boards for LinkedIn semiconductor design groups. The only trouble is engineers may have to move to get the jobs—sometimes halfway around the globe. There have been a bunch of job postings for semiconductor expertise in India, the United Kingdom, as well as pla... » read more

Fear Of Failure
By Ed Sperling - 05 Jun, 2009 - Comments: 0

For the past five decades, failure in the semiconductor world was nothing to be ashamed of. Mistakes were a sign of experience, and even some of the most spectacular errors in judgment didn’t cost design teams their jobs or deter more experimentation.   As we move down into the realm of 45nm and beyond, that’s no longer the case. Mistakes can cause an entire project to be shut down for... » read more

EUV Is Late—And It Hurts
By Ed Sperling - 28 May, 2009 - Comments: 0

Most chip architects and engineers couldn’t give a whit about the difference between deep ultraviolet and extreme ultraviolet lithography. It’s traditionally been a problem that foundries had to wrestle with, and that was their problem. Even DFM has been slow to catch on because what’s done in a foundry is of little interest up front.   The separation of those two worlds worked fine ... » read more

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