category: Technical Papers

category: Auto, Security & Edge AI

Overview: Ultra Ethernet’s Design and Architectural Advancements (ETH Zurich, Broadcom, HPE et al.)
By Technical Paper Link - 20 Aug, 2025 - Comments: 0

A new technical paper titled "Ultra Ethernet's Design Principles and Architectural Innovations" was published by researchers at ETH Zurich, Broadcom, Hewlett Packard Enterprise, OpenAI, Intel, Microsoft, AMD and Cisco. Abstract "The recently released Ultra Ethernet (UE) 1.0 specification defines a transformative High-Performance Ethernet standard for future Artificial Intelligence (AI) and ... » read more

Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes with High Core Density (Politecnico di Torino, imec et al.)
By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes" was published by researchers at Politecnico di Torino, EPFL, National Technical University of Athens and imec. Abstract "This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), address... » read more

Thermally-Aware, Multi-Objective Scheduling Framework for DL Workloads on Heterogeneous Multi-Chiplet PIM Architectures (UW–Madison, Washington State)
By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures" was published by researchers at the University of Wisconsin–Madison and Washington State University. Abstract "Chiplet-based integration enables large-scale systems that combine diverse technologies, enabling higher yield, lower costs, and sca... » read more

Scheduling Architecture Integrated With M3D BEOL Memories For LLM Inference (Georgia Tech, Samsung)
By Technical Paper Link - 19 Aug, 2025 - Comments: 0

A new technical paper titled "Architecting Long-Context LLM Acceleration with Packing-Prefetch Scheduler and Ultra-Large Capacity On-Chip Memories" was published by researchers at Georgia Institute of Technology and Samsung. Abstract "Long-context Large Language Model (LLM) inference faces increasing compute bottlenecks as attention calculations scale with context length, primarily due to t... » read more

Server-Scale Programmable Photonic Fabric to Interconnect Accelerators Within Servers (Cornell University, Lightmatter)
By Technical Paper Link - 15 Aug, 2025 - Comments: 0

A new technical paper titled "Morphlux: Programmable chip-to-chip photonic fabrics in multi-accelerator servers for ML" was published by researchers at Cornell University and Lightmatter. Abstract "We optically interconnect accelerator chips (e.g., GPUs, TPUs) within compute servers using newly viable programmable chip-to-chip photonic fabrics. In contrast, today, commercial multi-accelerat... » read more

Energy-Efficient Signal Detectors For Massive MIMO Using SRAM-Based IMCs (Univ. of Illinois at Urbana–Champaign)
By Technical Paper Link - 15 Aug, 2025 - Comments: 0

A new technical paper titled "Energy-Accuracy Trade-Offs in Massive MIMO Signal Detection Using SRAM-Based In-Memory Computing" was published by researchers at the University of Illinois at Urbana–Champaign. Abstract "This paper investigates the use of SRAM-based in-memory computing (IMC) architectures for designing energy efficient and accurate signal detectors for massive multi-input mu... » read more

Microservice-Based LLM Agents Enable EDA Flow Automation (Duke Univ. and Univ. of Maryland)
By Technical Paper Link - 15 Aug, 2025 - Comments: 0

A new technical paper titled "AutoEDA: Enabling EDA Flow Automation through Microservice-Based LLM Agents" was published by researchers at Duke University and University of Maryland. Abstract "Modern Electronic Design Automation (EDA) workflows, especially the RTL-to-GDSII flow, require heavily manual scripting and demonstrate a multitude of tool-specific interactions which limits scalabili... » read more

Power Gating Enabling in NPUs (Univ. of Illinois Urbana-Champaign)
By Technical Paper Link - 15 Aug, 2025 - Comments: 0

A new technical paper titled "ReGate: Enabling Power Gating in Neural Processing Units" was published by researchers at the University of Illinois Urbana-Champaign. Abstract "The energy efficiency of neural processing units (NPU) is playing a critical role in developing sustainable data centers. Our study with different generations of NPU chips reveals that 30%–72% of their energy consump... » read more

The Severity Of Test Escapes And SDCs Caused By Them (Google)
By Technical Paper Link - 15 Aug, 2025 - Comments: 0

A new technical paper titled "Silent Data Corruption by 10x Test Escapes Threatens Reliable Computing" was published by Google. Abstract "Too many defective compute chips are escaping existing manufacturing tests -- at least an order of magnitude more than industrial targets across all compute chip types in data centers. Silent data corruptions (SDCs) caused by test escapes, when left unadd... » read more

LtRAM And StRAM: Specialized Memory Architectures Leveraging Workload-Specific Access Characteristics (Stanford, Microsoft)
By Technical Paper Link - 12 Aug, 2025 - Comments: 0

A new technical paper titled "Towards Memory Specialization: A Case for Long-Term and Short-Term RAM" was published by researchers at Stanford University and Microsoft, and an independent researcher. Abstract "Both SRAM and DRAM have stopped scaling: there is no technical roadmap to reduce their cost (per byte/GB). As a result, memory now dominates system cost. This paper argues for a parad... » read more

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