category: Technical Papers

category: Auto, Security & Edge AI

CP-Based Lot Scheduling Solutions For a Semiconductor Manufacturing (Infineon, U. of Klagenfurt)
By Technical Paper Link - 31 Mar, 2026 - Comments: 0

A new technical paper, "Quantifying the Global Impact of Constraint Programming Based Local Scheduling in Semiconductor Manufacturing," was published by Infineon and the University of Klagenfurt. Abstract "The efficiency of semiconductor frontend manufacturing highly depends on the optimization of resource allocation. In academic works, scheduling methods, i.e., based on Constraint Progra... » read more

Simulations of Silicon Spin Qubits Based on a GAAFET (Teikyo U., Riken)
By Technical Paper Link - 30 Mar, 2026 - Comments: 0

A new technical paper, "Device/circuit simulations of silicon spin qubits based on a gate-all-around transistor," was published by Teikyo University and RIKEN. Abstract "We theoretically investigated the readout process of a spin–qubit structure based on a gate-all-around (GAA) transistor. Our study focuses on a logical qubit composed of two physical qubits. Different spin configuration... » read more

Integrating Error Propagation Theory Into the FMEDA Framework (Robert Bosch GmbH)
By Technical Paper Link - 27 Mar, 2026 - Comments: 0

A new technical paper, "Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification," was published by Robert Bosch GmbH. Abstract "Accurate and reliable safety metrics are paramount for functional safety verification of ASICs in automotive systems. Traditional FMEDA (Failure Modes, Effects, and Diagnostic Analysis) metrics, such as SPFM (... » read more

In-Depth Analysis of 187 Publications on Hardware Reverse Engineering (Ruhr U., MPI)
By Technical Paper Link - 27 Mar, 2026 - Comments: 0

A new technical paper, "SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research," was published by the Ruhr University Bochum and the Max Planck Institute for Security and Privacy. Abstract "As hardware serves as the root of trust in modern computing systems, Hardware Reverse Engineering (HRE) is foundational for security assurance. In practice, HRE en... » read more

Systematic Analysis of CPU-Induced Slowdowns in Multi-GPU LLM Inference (Georgia Tech)
By Technical Paper Link - 27 Mar, 2026 - Comments: 0

A new technical paper, "Characterizing CPU-Induced Slowdowns in Multi-GPU LLM Inference," was published by the Georgia Institute of Technology. Abstract "Large-scale machine learning workloads increasingly rely on multi-GPU systems, yet their performance is often limited by an overlooked component: the CPU. Through a detailed study of modern large language model (LLM) inference and servin... » read more

How SW and HW Vulnerabilities Can Complement LLM-Specific Algorithmic Attacks (UT Austin, Intel et al.)
By Technical Paper Link - 20 Mar, 2026 - Comments: 0

A new technical paper, "Cascade: Composing Software-Hardware Attack Gadgets for Adversarial Threat Amplification in Compound AI Systems," was published by the University of Texas, Austin, Intel Labs, Symmetry Systems, Microsoft and Georgia Tech. Abstract "Rapid progress in generative AI has given rise to Compound AI systems - pipelines comprised of multiple large language models (LLM), so... » read more

Bias- and Temperature-Dependent Noise Measurements to Investigate Carrier Transport at the Tellurium Interface (POSTECH)
By Technical Paper Link - 20 Mar, 2026 - Comments: 0

A new technical paper, "Revealing and Engineering Contact-Origin Noise in Ultrathin Tellurium Transistors," was published by researchers at Pohang University of Science and Technology. Abstract "Tellurium (Te) has emerged as a promising p-type semiconductor for ultrathin electronics owing to its strong air stability, excellent hole transport, narrow bandgap, and BEOL-integration compatibi... » read more

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)
By Technical Paper Link - 18 Mar, 2026 - Comments: 0

A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Identifying Read Disturbance Threshold of DRAM Chips (ETH Zurich, Rutgers)
By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips," was published by ETH Zurich and Rutgers University. Abstract "State-of-the-art DRAM read disturbance mitigations rely on the read disturbance threshold (RDT) (e.g., the number of aggressor row activations needed to induce the first read disturba... » read more

Analysis of the Evolving Landscape of Ultra-low-power Edge AI Processors (U. of Austria, ETH Zurich)
By Technical Paper Link - 17 Mar, 2026 - Comments: 0

A new technical paper, "Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review," was published by University of Austria and ETH Zurich. Abstract "This review examines the rapidly evolving landscape of ultra-low-power edge processors, covering heterogeneous Systems-on-Chips (SoCs), neural accelerators, near-sensor and in-sensor architectures, and emerging dataflow a... » read more

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