Scramble For The White Space


Chipmakers are pushing to utilize more of the unused portion of a design for different functions, reducing margin in the rest of the chip to more clearly define that white space. White space typically is used to relieve back-end routing congestion before all of the silicon area is used up. But a significant amount of space still remain unused. That provides an opportunity for inserting monit... » read more

The Quest To Make 5G Systems Reliable


Semiconductor Engineering sat down to discuss 5G reliability with Anthony Lord, director of RF product marketing at FormFactor; Noam Brousard, system vice president at proteanTecs; Andre van de Geijn, business development manager at yieldHUB; and David Hall, head of semiconductor marketing at National Instruments. What follows are excerpts of that conversation. SE: How do we measure the reli... » read more

New Data Format Boosts Test Analytics


Demand for more and better data for test is driving a major standards effort, paving the way for one of most significant changes in data formats in years. There is good reason for this shift. Data from device testing is becoming a critical element in test program decisions regarding limits and flows. This is true for everything from automotive and medical components to complex, heterogeneous... » read more

Better Inspection, Higher Yield


Wafers can be inspected for large, obvious defects, or for small, subtle ones. The former is referred to as macro-inspection, while the latter is micro-inspection. These processes use different machines with different capital and operating costs, and they might look like competing approaches with different economic returns. In fact, they are complementary tactics that can be balanced within an ... » read more

Far Out AI In Remote Locations


There really isn’t anything that you can do on Earth with electronics that you can’t do in space, but it certainly can be a lot harder and take longer to fix is something goes wrong. And as more intelligent electronics are launched into space, the concern over potential failures is growing. AI inferencing has been pushing out further for some time, and it is starting to redefine what con... » read more

Chiplet Reliability Challenges Ahead


Assembling chips using LEGO-like hard IP is finally beginning to take root, more than two decades after it was first proposed, holding the promise of faster time to market with predictable results and higher yield. But as these systems of chips begin showing up in mission-critical and safety-critical applications, ensuring reliability is proving to be stubbornly difficult. The main driver fo... » read more

Better Analytics Needed For Assembly


Package equipment sensors, newer inspection techniques, and analytics enable quality and yield improvement, but all of those will require a bigger investment on the part of assembly houses. That's easier said than done. Assembly operations long have operated on thin profit margins because their tasks were considered easy to manage. Much has changed over the past several years, however. The r... » read more

5G Brings New Testing Challenges


As 5G nears commercial reality, makers of chips and systems that will support 5G will need to take on the standard burden of characterizing and testing their systems to ensure both performance and regulatory adherence. Millimeter-wave (mmWave) and beamforming capabilities present the biggest testing challenges. “5G is expected to have the extended coverage plus the bandwidth to harness ... » read more

Auto Chip Reliability Opens Door To Other Industries


Digital chips in the semiconductor industry evolve from each other. Ideas flow into each other over the years, with occasional big leaps in evolution. The term ‘evolution’ fits because one chip evolves to perfectly optimized for one industry niche. But what happens when one industry’s chip becomes a useful for other industries because it is more cost-effective than what is being used i... » read more

Advanced Packaging Makes Testing More Complex


The limits of monolithic integration, together with advances in chip interconnect and packaging technologies, have spurred the growth of heterogeneous advanced packaging where multiple dies are co-packaged using 2.5D and 3D approaches. But this also raises complex test challenges, which are driving new standards and approaches to advanced-package testing. While many of the showstopper issues... » read more

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