category: Top Stories

category: Auto, Security & Edge AI

End-User Report: Interoperability Still Lacking With System-Level Power Modeling
By Ann Mutschler - 27 Aug, 2009 - Comments: 0

All of the major EDA vendors and standards groups are pitching modeling as the next level of abstraction for advanced process nodes, but is it working as planned for the chipmakers? System-Level Design caught up with Frans Theeuwen, Department Manager for System Design at NXP Semiconductors Corp. to discuss system-level design and power modeling. By Ann Steffora Mutschler SLD: How long has N... » read more

More Cores, Different Approaches
By Ed Sperling - 27 Aug, 2009 - Comments: 0

By Ed Sperling The general consensus among software developers is that some applications will never be able to take advantage of multiple cores, but that certainly doesn’t mean system designers can’t figure out ways to use more cores. Nor does it mean that all cores are created equal. The picture that is emerging from multiple chipmakers shows the following trends: More cores have lim... » read more

Hot Chips 2009: It’s All About Multicore And Low-Power
By Pallab Chatterjee - 27 Aug, 2009 - Comments: 0

By Pallab Chatterjee The game has changed for processors. The goal now is data throughput, not higher gigahertz and more watts. That shift dominated the presentations at the Hot Chips conference this week. In previous years, the theme was higher single-core performance, more power and smaller geometries processes. This year it was all about multi-core and multi-power options as the realities ... » read more

3D Integration: Extending Moore’s Law Into The Next Decade
By Cheryl Ajluni - 27 Aug, 2009 - Comments: 0

By Cheryl Ajluni At the 46th Design Automation Conference in San Francisco last month, attention turned to a discussion of how to extend the momentum of Moore’s Law into the next decade. One plausible solution, according to Philippe Magarshack, the general manager of Central CAD & Design Solutions at STMicroelectronics, is 3D stacking for complex System-on-Chips (SoCs). The concept of 3... » read more

Restrictive Design Rules, Take Two
By Ed Sperling - 27 Aug, 2009 - Comments: 0

By Ed Sperling For the past couple of years, restrictive design rules have been looming over advanced process nodes as the best way to get a chip out the door with minimal re-spins, on schedule and for the least amount of money. Even with immersion technology, 193nm wavelengths mean the laser beam is entirely too large to create the masks used to create complex systems on chip at 32nm and bel... » read more

When It Comes To Intellectual Property, Size Matters
By Various Writers - 19 Aug, 2009 - Comments: 0

By Geoffrey James Intellectual property was once seen as the new growth market for EDA. Dozens of firms – large and small – jumped on the IP bandwagon, attracted to the “build once, sell many times” business model. “As late as 2004, the industry was still thinking that as much as 90% of SoCs would be reused IP,” said EDA consultant Gary Smith. The IP segment, however, hasn�... » read more

Who’s In Control Now?
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Power is shifting across the design industry in multiple ways and sometimes across multiple continents, driven by complexity and cost pressures and entirely new forms of competition. On one side of the equation, foundries are dictating more of what goes on up front in the design cycle. Design for manufacturing is a prerequisite at 45nm and below, and they’re the ones dictatin... » read more

To Bus Or Not To Bus, That Is The Question
By Ann Mutschler - 31 Jul, 2009 - Comments: 0

By Ann Steffora Mutschler When you hear the words, “block interface,” your ears may not perk up, but as system architects well understand, making the right choice between a bus or non-bus interface on an SoC is absolutely critical to design’s success in terms of power efficiency, reusability and performance. How many of the problems in new chip designs have to do with the interconne... » read more

ESL: Reality, Or A Pigment Of Your Fig Neuton?
By Various Writers - 31 Jul, 2009 - Comments: 0

By Clive "Max" Maxfield One of the questions I am often asked is: "Who's really using ESL tools such as modeling and are there any hiccups in the flow?" Another common question is: "What actually is ESL?" Perhaps we should address the latter question first. To some folks, ESL (electronic system level) means designing at a very high level of abstraction prior to making any hardware-softwar... » read more

Boost For Verification Methodologies
By Ed Sperling - 31 Jul, 2009 - Comments: 0

By Ed Sperling Synopsys introduced enhancements to its Verification Methodology Manual and Cadence began detailing new enhancements in its Open Verification Methodology. Both programs are in beta, yet they offer steps forward toward easing one of the biggest problem areas in chip development. With verification still consuming 70% or more of the non-recurring engineering costs of semicondu... » read more

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