category: Top Stories

category: Auto, Security & Edge AI

Defining Sufficient Coverage
By Brian Bailey - 24 Nov, 2015 - Comments: 2

Semiconductor Engineering sat down to discuss the definition of sufficient coverage as a part of verification closure with Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"], Willard Tu, director of embedded segment marketing for [getentity id="22186" comment="ARM"], Larry Vivolo (who at the time of this roundtable was senior director of product marketing for [gete... » read more

Fan-Out Packaging Gains Steam
By Mark LaPedus - 23 Nov, 2015 - Comments: 1

Fan-outs are creating a buzz and gaining steam in the market at a pace far beyond what anyone would have expected even at the start of the year. The approach, which has been around for several years, is a wafer-level packaging process that enables ultra-thin, high-density packages. So why the buzz? Apple is apparently moving to [getkc id="202" kc_name="fan-out"] packaging, according to an... » read more

Can Nano-Patterning Save Moore’s Law?
By Mark LaPedus - 19 Nov, 2015 - Comments: 0

For years the academic community has explored a novel technology called selective deposition. Then, more than a year ago, Intel spearheaded an effort to bring the technology from the lab to the fab at 7nm or 5nm. Today, selective deposition is still in R&D, but it is gaining momentum in the industry. With R&D funding from Intel and others, selective deposition, sometimes called ALD-e... » read more

Why Packaging Matters
By Ed Sperling - 19 Nov, 2015 - Comments: 1

The semiconductor package is changing. What was until very recently considered an afterthought is now becoming a key part of the design process at all major chipmakers, and a critical factor in the extension of Moore's Law. This is a sharp reversal of what was almost universally an afterthought in planar silicon design and manufacturing. Rarely was the package an integral part of the archite... » read more

Measuring FinFETs Will Get Harder
By Mark LaPedus - 19 Nov, 2015 - Comments: 2

The industry is gradually migrating toward chips based on finFET transistors at 16nm/14nm and beyond, but manufacturing those finFETs is proving to be a daunting challenge in the fab. Patterning is the most difficult process for finFETs. But another process, metrology, is fast becoming one of the biggest challenges for the next-generation transistor technology. In fact, [getkc id="252" kc_n... » read more

Inside Multi-Beam E-Beam Lithography
By Mark LaPedus - 19 Nov, 2015 - Comments: 4

Semiconductor Engineering sat down with David Lam, chairman of Multibeam, a developer of multi-beam e-beam tools for direct-write lithography applications. Lam is also a venture capitalist. He founded Lam Research in 1980, but left as an employee in 1985. What follows are excerpts of that conversation. SE: How has the equipment business changed over the years and what’s the state of the i... » read more

What’s Really Causing Line-Edge Roughness?
By Katherine Derbyshire - 19 Nov, 2015 - Comments: 0

As previously discussed, shot noise is an important contributor to line edge roughness. However, as the title of one paper on the subject put it, “Do not always blame the photons.” The line edge roughness of a chemically amplified resist ultimately depends on photoacid generation and the deprotection of the resist’s base monomers. Photons absorbed by the resist simply trigger a chain ... » read more

Do Circuits Whisper Or Shout?
By Ann Mutschler - 18 Nov, 2015 - Comments: 0

Maximizing SoC performance and minimizing power is becoming a multi-layered and multi-company challenge that depends on everything from ecosystem feedback and interactions to micro-architectural decisions about whether analog circuits whisper or shout. What used to be a straightforward architectural tradeoff between performance and power has evolved into a much more diffuse and collaborativ... » read more

Placing Bets On Future Technology
By Ed Sperling - 16 Nov, 2015 - Comments: 0

Marie Semeria, CEO of Leti, sat down with Semiconductor Engineering to talk about where the French research and technology organization is placing its future technology bets and what's behind those decisions. What follows are excerpts of that discussion. SE: It's becoming more difficult and expensive to shrink features, so where do we go next? Semeria: We see several areas that we believe... » read more

The Cloud, The IoE, And You
By Ernest Worthman - 13 Nov, 2015 - Comments: 0

In part one, the cloud of the future was dissected. This part examines concerns and possible impediments. No one doubts the cloud will be an important part of the Internet of Everything, but the transition from local to off-site computing will never be completely seamless or risk-free. To begin with, there is the cost of storage and bandwidth. Running applications using on-site hardware ... » read more

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