Security Risks Grow Worse


Semiconductor Engineering sat down to discuss security issues for connected devices with Marc Canel, vice president of security at [getentity id="22186" comment="ARM"]; Paul Kocher, president and chief scientist for the Cryptography Research division of [getentity id="22671" e_name="Rambus"]; Michael Poitner, global segment marketing manager at [getentity id="22499" e_name="NXP"]; Felix Baum, h... » read more

Hybrid Verification: The Only Way Forward


Semiconductor Engineering sat down to discuss the state of the industry for [getkc id="10" kc_name=" functional verification"]. The inability of RTL [getkc id="11" kc_name="simulation"] to keep up with verification needs is causing rapid change in the industry. Taking part in the discussion are Harry Foster, chief scientist at [getentity id="22017" e_name="Mentor Graphics"]; Janick Bergeron, fe... » read more

Is The Stacked Die Ecosystem Stagnating?


While the stacked die ecosystem in general is currently status quo, with not much happening in the past year, there is definitely work being done —albeit cautiously—on the design tools side of things. It would be easy to feel impatient that the design tools are not complete and available today for [getkc id="82" comment="2.5D"] and [getkc id="42" comment="3D IC"] implementation until hearin... » read more

Industry Scorecard For 2014


At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Part one addressed the market and semiconductor areas and in thi... » read more

Integrating DSA


As previous articles in this series have shown, directed self-assembly may be a promising alternative for manufacturers seeking to shrink feature sizes in the face of a stalled exposure tool roadmap. It is simpler than some other frequency-multiplication techniques, can be implemented with existing equipment, and does not appear to introduce insurmountable defect issues of its own. Which does n... » read more

DSA Moves Ahead


It can be difficult to make DSA structures other than uniform arrays. One solution is to print a grating over a large area, then use a “cut” mask to eliminate the unwanted features. The challenge, though, is that aligning the cut mask to an array of tightly spaced features, such as the fins for a FinFET transistor layer, can require extremely demanding overlay specifications. While reducing... » read more

Unraveling The Mysteries At IEDM


In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D IC"] chips, III-V materials, [getkc ... » read more

Industry Scorecard For 2014


At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Markets The obvious trend, at the beginning of the year, wa... » read more

Trouble Spots And Optimism For 2015


Most top executives in the semiconductor industry are bullish about 2015 and even beyond, particularly as the [getkc id="76" comment="Internet of Things"] begins to drive new markets and market mash-ups, and as more semiconductors find their way into markets such as automotive, health-care and manufacturing. But it's not an entirely rosy picture, and top executives point to potential trouble sp... » read more

Is The Stacked Die Ecosystem Stagnating?


It is now widely agreed that not much has been happening in terms of adoption for 2.5D interposer and 3D ICs. “It seems like everyone is still at the starting line waiting for the race to begin," said Javier DeLaCruz, senior director of engineering of [getentity id="22242" e_name="eSilicon"]. "Interposer assembly and IP availability for effectively using the [getkc id="82" comment="2.5D IC... » read more

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