Hardware-Software Rift Persists


Last month Semiconductor Engineering published an article about power optimization and the roles of the hardware and software teams in reducing energy consumption. The article portrayed the hardware team adding lots of capabilities for power reduction, while the software team was not making full use of those capabilities. That article made the rounds in a couple of LinkedIn forums populated ... » read more

Heat Problems Grow With FinFETs, 3D-ICs


From high-end consumer devices to rack-mounted arrays inside of data centers, thermal issues are becoming more serious—and getting much more attention. Driving this shift is the move from single chips to 3D ICs, whether they are interposer-based or stacked die. It’s a well-understood challenge: Die stacking can cause thermal issues because of the lack of a readily accessible thermal diss... » read more

The List Of Unknowns Grows After Silicon


As discussed earlier in this series, most proposed alternative channel schemes depend on germanium channels for pMOS transistors, and InGaAs channels for nMOS transistors. Of the two materials, InGaAs poses by far the more difficult integration challenges. Germanium has been present in advanced silicon CMOS fabs for several technology generations, having been introduced used in strained silicon... » read more

NAND ATE Market Gets Testy


The NAND flash memory market is undergoing big changes. As planar NAND moves further down the 1xnm node regime, suppliers are ramping up devices with new cell structures, interfaces and other features. And on top of that, 3D NAND is beginning to appear in the market. The next-generation NAND devices will enable new applications in the mobile and enterprise markets, but the chips themselves p... » read more

Cadence To Buy Forte


Cadence agreed to buy Forte Design Systems for an undisclosed sum, enhancing its footprint in the high-level synthesis market as higher levels of abstraction gain traction across the SoC world. For the better part of a decade high-level synthesis (HLS) has been a market opportunity that was just around the next bend, along with electronic system-level design and SystemC modeling. Mentor Grap... » read more

Expert Interview: NXP On Security


Semiconductor Engineering sat down with Mathias Wagner, NXP fellow and chief security technologist, to discuss the challenges in securing SoCs. SE: Can we ever get a really firm handle on security issues in SoCs? Wagner: No. There are too many papers on attacks and countermeasures that come out every year. In the embedded security field alone there are about 100 papers every year, so if y... » read more

The Next Big Threat: System Security


No SoC ever will be totally secure, and no technology will stop experienced thieves who really want to get into a device. But chipmakers and IP companies are examining ways to at least make it more difficult—and at least in theory, far less lucrative. One big change, of course, is that a connected electronic ecosystem has made location irrelevant. In the past, crime was limited to where th... » read more

The Uncertain Future Of Fabless Semis


As with most things, perspective is everything, this is especially true when it comes to changes in the semiconductor ecosystem. Some industry watchers say indicators clearly point to a shift happening where system OEMs again make the decisions about what is in a chip, both software and hardware, pointing to Apple, Samsung, Microsoft and Intel as prime examples. As a result, the fabless semicon... » read more

Patents Under Scrutiny


After years of complaints by high-tech companies that the U.S. patent system is misused, too slow or completely outdated, patent attorneys are about to get their day in court. The U.S. Supreme Court has agreed to review an appeal between Alice Corp., an electronic marketplace for trading IP, and CLS Bank International, involving what kinds of inventions can be patented, according to the Supr... » read more

The Growing Verification Challenge


As complexity continues to mount in designing SoCs, so does the challenge of verifying them within the same time window and using the same compute and engineering resources. Chipmakers aren’t always successful at this. In many cases they have to put more engineers on the verification and debug at the tail end of a design to get it out the door on or close to schedule. In many cases that al... » read more

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