category: Top Stories

category: Auto, Security & Edge AI

Standards Update
By Ann Mutschler - 18 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler In the sometimes-murky waters of system-level modeling standards where real-world adoption can be difficult to track, work is progressing to help hardware and software engineers realize the promise of true hardware-software codesign. The three main standards efforts related to modeling at the system level are OSCI’s TLM-2.0, OCP-IP’s OCP and Open Modeling TAB a... » read more

Reducing Bottlenecks
By Ann Mutschler - 18 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler For the first time ever, China recently earned fastest supercomputer bragging rights with its Tianhe-1A supercomputer, which can perform 2.57 quadrillion computing operations per second. The machine has been successfully used to survey mines, forecast weather and design high-end machinery. While it has caused concern, it is important to note that the Tianhe-1A use... » read more

Building Up In 3D
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Stacked die are expected to begin showing up in volume in late 2012 and in 2013, turning what has been a science experiment into a mainstream way of designing and manufacturing SoCs. This magnitude of this shift cannot be overstated, and clearly all of the pieces are not in place to make it all happen immediately. There also are significant technology challenges to overcome, ... » read more

Verifying At The System Level
By Ed Sperling - 18 Nov, 2010 - Comments: 0

By Ed Sperling Verification has always been the problem child of SoC design. It requires the most engineering resources, the largest block of time and the biggest budget in the design process. And at each new process node the problem gets bigger, in part because there is more stuff on each die—transistors, memory, interconnects, I/O, functionality—and in part because chipmakers are being c... » read more

ARM’s Race
By Ed Sperling - 05 Nov, 2010 - Comments: 0

Prior to the Synopsys acquisition of Virage Logic, Synopsys seemed to have an almost exclusive relationship with ARM. Since then, Cadence and Mentor Graphics have both been cutting deals with ARM for support of its IP cores. What’s changed? With regard to the Virage Logic acquisition, very little. Synopsys did acquire the ARC processor through that deal, but ARC had been much more focused ... » read more

The Trouble With Low-Power Verification
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling If verification accounts for 70% of the non-recurring engineering expenses in a design, what percentage does verifying a low-power design actually consume? Answer: No one knows for sure. The reason has more to do with insufficient data than tools, processes or flows. That’s also the reason that power models have never been created for more than a single design. “Power... » read more

How Software Utilizes Cores
By Ed Sperling - 04 Nov, 2010 - Comments: 2

By Ann Steffora Mutschler When writing software, how does the design engineer determine how much power it will draw on a particular targeted platform? While the question seems straightforward, the answer is not. The industry is just starting to develop the ability to get some data in that space, according to Cary Chin, director of technical marketing for Synopsys’ low-power solutions gr... » read more

Low-Power Standards Watch: Ethernet
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Colleen Taylor With a job that can legitimately count "the inherent constraints of quantum physics" as a major cause of workplace stress, engineers in the semiconductor industry have never exactly had it easy. But as policymakers focused on curbing emissions impose increasingly strict regulations on the power consumption of consumer electronic devices, a host of new challenges have emerged ... » read more

Power-Delivery Network Challenges Grow
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ann Steffora Mutschler Physics is forcing convergence in the SoC power delivery network, whose job is to ensure that every device on a chip has a robust and stable voltage so it can meet its expected functionality and timing. In the past, chip design, package design and board design were separate disciplines, guard-banded to ensure that all the parts worked well together. Today, given t... » read more

Making Software More Efficient
By Ed Sperling - 04 Nov, 2010 - Comments: 0

By Ed Sperling Software is being targeted by most of the major chip vendors and EDA companies as the next big opportunity for saving power, but exactly which software should be modified and by whom isn’t always clear. To some extent those answers depend upon which part of the software stack vendors or engineers believe can be adjusted most easily, and so far there is no widespread agreeme... » read more

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