category: Top Stories

category: Auto, Security & Edge AI

Qualcomm Shies Away From High-k At 28nm
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By David Lammers Qualcomm CDMA Technologies said it will not use a high-k/metal gate (HKMG) process for most of the chips it makes at the 28 nm node, sticking with a poly/SiON gate stack. The company described the rationale behind the strategy, which because of Qualcomm’s size will have a major impact on the foundry business, at the 2010 International Electron Devices Meeting (IEDM) held in ... » read more

Version Control Nightmares
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Ed Sperling The rampant re-use of IP and the growing reliance on software to smooth over glitches is creating a nightmare in version control of everything from IP blocks to EDA tools. Version control has always been a problem in SoC design, of course. Tools have to be in sync with engineering teams that are spread across multiple continents and working on different pieces of the design e... » read more

System-Level Technology Conversations Shift To Deployment
By Ann Mutschler - 16 Dec, 2010 - Comments: 0

While much has been achieved to define a system-level design flow, more is still needed. Technology goals vary depending on the perspective of tool providers in terms of what needs to be done to realize the promise of a streamlined tool flow from TLM 2.0 down to GDS II. To many, 2011 will be an interesting year in the system-level design space as conversations with customers have shifted. �... » read more

New 3D Stacking Techniques Emerge
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Pallab Chatterjee To take advantage of the capabilities of the new technologies, design and circuit architectures in the future will have to be closely coupled with the basic device creation. That shift was the subject of a special session at the recent IEDM conference focusing on the confluence of technology and design. One such area under discussion involved 3D ICs. While a lot of disc... » read more

The Rising Stake In Software Tools
By Ed Sperling - 03 Dec, 2010 - Comments: 0

By Ed Sperling The growing importance of software and off-the-shelf IP in semiconductor design is beginning to change the dynamics of the entire EDA tools business, setting off a string of acquisitions as the largest players realign themselves to take advantage of this shift. The most recent example: Mentor Graphics’ acquisition this week of CodeSourcery, a GNU-based Linux toolchain and s... » read more

The Deafening Problem Of High-Speed I/O
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler The performance of digital systems today is limited by the interconnection bandwidth between chips, boards, and cabinets. This has driven I/O speeds up into the gigabytes. While this boosts performance, it also opens the door to a host of new problems within the chip, board and system. Add low-power requirements to the mix and it is a recipe for huge headaches. One... » read more

Race Intensifies To Develop EUV Source
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By David Lammers The technology competition to supply the source of EUV radiation for the next-generation lithography tools has long been divided between the laser-produced plasma (LPP) approach, favored by Cymer (San Diego) and Gigaphoton (Oyama, Japan), and the discharge -produced plasma (DPP) method supported by Xtreme Technologies (Aachen, Germany). The competition is heating up, and it... » read more

3D Stacked Die Create Unique Test Issues
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler While 3D die stacking promises a number of benefits including smaller footprint, faster speed, lower power and possibly lower cost, testing those devices isn’t going to be simple. There are varying degrees of challenges aligned with varying types of defects that occur throughout the process, from wafer fabrication to package assembly to system-level assembly. And... » read more

The Growing Legacy Of Moore’s Law
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Ed Sperling Moore’s Law has defined semiconductor design since it was introduced in 1965, but increasingly it also has begun defining the manufacturing equipment, the cooling needed for end devices, and both the heat and performance of systems. In the equipment sector the big problem has been the delay in rolling out extreme ultraviolet (EUV). Moore’s Law will require tighter spacing... » read more

Power Optimization Below 28nm
By Ed Sperling - 02 Dec, 2010 - Comments: 0

By Pallab Chatterjee Process scaling has normally been performed on a lithographic basis, but as processes dip below 32nm there are optimization options beyond the lithographic and area reduction. The Common Platform Group and GlobalFoundries have added the tradeoffs of power and performance optimization in addition to area in their 28nm flows. TSMC uses a five-way optimization that also h... » read more

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