Automated Conversion Of Xilinx Vivado Projects To ALINT-PRO


Aldec's ALINT-PRO design verification solution performs static RTL and design constraints code analysis to uncover critical design issues early in the design cycle. The product helps FPGA developers rise to the challenge of designing large FPGA designs and multiprocessor system on chip devices that include high-capacity and high-performance FPGA hardware. The solution supports running rule c... » read more

Parallel RTL Exploration With Unparalleled Accuracy


Increasing chip complexity and restrictive advanced node rules have made it harder for implementation tools to achieve PPA targets and node entitlements via last-mile optimizations. RTL Architect enables designers to "shift-left" and predict the implementation impact of their RTL. RTL designers, SoC integrators, and IP developers have embraced this fast, predictive technology to give them new i... » read more

RF To Millimeter-Wave Front-End Component Design Trends For 5G Communications


This white paper discusses design challenges and solutions related to the "third wave" of communications, presenting several case studies in which the Cadence AWR Design Environment platform has been used to develop products for 5G and beyond. Examples include a multiband active antenna tuner for cellular internet of things (IoT) machine-type communications (mMTC) applications, a linear power a... » read more

A Methodology To Verify Functionality, Security, And Trust for RISC-V Cores


Modern processor designs present some of the toughest hardware verification challenges. These challenges are especially acute for RISC-V processor core designs, with a wide range of variations and implementations available from a plethora of sources. This paper describes a verification methodology available to both RISC-V core providers and system-on-chip (SoC) teams integrating these cores. It... » read more

Underlayer Optimization Method For EUV Lithography


Photoresist and underlayer combine to serve a central role in EUVL for patterning. Layers will be very thin in future, because high numerical aperture (NA) and tight pitches will require very thin layers in the lithography stack. This thinness will make chemical interactions at the photoresist-underlayer interface more common. Adhesion between these layers will be critical to overcome pattern c... » read more

Survey: 2020 eBeam Initiative Annual Survey Results


Aki Fujimura, the CEO of D2S, Inc. presented "The eBeam Initiative's Annual Survey Results at Photomask" at Photomask Japan 2021 in April 2021. Survey says that COVID has a net neutral business impact on total mask revenues. By 2021, 24% positive vs 20% negative COVID-related business predictions. 74% agree actinic inspection for EUV HVM by 2023, and more results. Click here to read more. » read more

Will An Adhesion Promoter Prevent Delamination In Power Semiconductor Packages?


Power semiconductor packages are used in high temperature, high voltage environments. With the increase of electric vehicles (EVs) and hybrid electric vehicles (HEV) in the automotive market, demands on (and for) power packages have been growing. Packages for automotive applications must pass extensive testing for safety, therefore, packaging reliability is essential. As more semiconductor pack... » read more

Innovative Dual Mark Design For Alignment Verification And Process Monitoring In Advanced Lithography


Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, it is possible to determine intra-wafer distortion wafer-by-wafer. Both the measurement and modeled results are applied directly as a feed-forward correction to enable wafer level control. In this p... » read more

The Effects Of Poly Corner Etch Residue On Advanced FinFET Device Performance


In this paper, we study the effect of poly corner residue during a 5nm FinFET poly etch process using virtual fabrication. A systemic investigation was performed to understand the impact of poly corner residue on hard failure modes and device performance. Our results indicate that larger width and height residues can lead to a hard failure by creating a short between the source/drain epitaxy an... » read more

Streaming Scan Network


The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. In the traditional approach to delivering scan test data to cores, each core requires a dedicated connection to chip-level pins, which doesn’t allow for much flexibility, as the dependencies betwee... » read more

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