category: Videos

category: Auto, Security & Edge AI

Security In FPGAs And SoCs
By Ed Sperling - 23 Feb, 2021 - Comments: 0

Chip security is becoming a bigger problem across different markets, with different emerging standards and more sophisticated attacks. Jason Moore, senior director of engineering at Xilinx, talks with Semiconductor Engineering about current and future threats and what can be done about them. » read more

Securing ICs With Information Flow Analysis
By Ed Sperling - 16 Feb, 2021 - Comments: 0

Following the data has new meaning when it comes to security. Alric Althoff, senior hardware security engineer at Tortuga Logic, talks about tracking the flow of data through a hardware design over time, including what happens with roots of trust, how this works with existing tools and methodologies, and what to think about when tracing potential security risks. » read more

IP Safe Enough To Use In Cars
By Ed Sperling - 07 Dec, 2020 - Comments: 0

IP that is used for functional safety needs to respond to events that can happen, whether those are planned or random. Jody Defazio, vice president of IP quality and functional safety at Synopsys, talks with Semiconductor Engineering about ASIL compliance, what the different levels mean, and the impact of using chips developed at the most advanced process nodes in automotive applications. » read more

Faster Inferencing At The Edge
By Ed Sperling - 09 Nov, 2020 - Comments: 0

Cheng Wang, senior vice president of engineering at Flex Logix, talks about inferencing at the edge, what are some of the main considerations in designing and choosing an inferencing chip, why programmability and modularity are important, and how hardware-software co-design with algorithms can improve performance and power. » read more

AI Inference Acceleration
By Ed Sperling - 14 Sep, 2020 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks about considerations in choosing an AI inference accelerator, how that fits in with other processing elements on a chip, what tradeoffs are involved with reducing latency, and what considerations are the most important. » read more

Memory Access In AI Systems
By Ed Sperling - 27 Jul, 2020 - Comments: 0

Memory access is a key consideration in AI system design. Ron Lowman, strategic marketing manager for IP at Synopsys, talks about how memory affects overall power consumption, why partitioning of on-chip and off-chip is so critical to performance and power, and how this changes from the cloud to the edge. » read more

eFPGAs Vs. FPGA Chiplets
By Ed Sperling - 22 Jul, 2020 - Comments: 0

Embedded FPGAs are a totally different concept from discrete FPGA chiplets, and that is reflected in size, cost, power and performance. Geoff Tate, CEO of Flex Logix, talks about which applications are best for each, how each maximizes power and performance, and why choices will vary greatly by application. Related eFPGA Knowledge Center FPGA Knowledge Center Increasing EFPGA Densit... » read more

3 Types Of AI Hardware
By Ed Sperling - 20 Jul, 2020 - Comments: 1

As AI chips become more pervasive, three primary approaches are moving to the forefront. Bradley Geden, director of product marketing at Synopsys, looks at how to take advantage of repeatability, what the different flavors look like, the difference between flat and hierarchical design, and what impact black-box arrays have on programmability. » read more

Increasing eFPGA Density
By Ed Sperling - 24 Jun, 2020 - Comments: 0

How to boost embedded FPGA density to the point where it is competitive with traditional FPGAs, at a lower cost and faster turnaround time. Geoff Tate, CEO of Flex Logix, talks about the importance of interconnects and standard cells in adding flexibility into chips, and why eFPGAs are suddenly gaining attention. » read more

Different Levels Of Interconnects
By Ed Sperling - 17 Jun, 2020 - Comments: 0

The interconnect hierarchy from metal 0 in a semiconductor all the way up to racks of servers. Kurt Shuler, vice president of marketing at Arteris IP, explains why each one is different, and how every level can contribute to latency and performance. » read more

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