category: Videos

category: Auto, Security & Edge AI

DAC 2020: Virtual And Different
By Ed Sperling - 08 Jun, 2020 - Comments: 0

Zhuo Li, group director at Cadence, and Harry Foster, chief scientist at Mentor, a Siemens Business, talk about the changes in content for this year's Design Automation Conference. » read more

Big Changes For eFPGAs
By Ed Sperling - 11 May, 2020 - Comments: 0

Geoff Tate, CEO of Flex Logix, talks with Semiconductor Engineering about the state of embedded FPGAs, why this is easier for some companies than others, why this is important for adding flexibility into an ASIC, and what are the main applications for this technology. » read more

Who Owns A Car’s Chip Architecture
By Ed Sperling - 05 May, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, examines the competitive battle brewing between OEMs and Tier 1s over who owns the architecture of the electronic systems and the underlying chip hardware. This has become a growing point of contention as both struggle for differentiation in a market where increasingly autonomous vehicles will all behave the same way. That, in turn, has si... » read more

DDR PHY Training
By Ed Sperling - 21 Apr, 2020 - Comments: 0

Brett Murdock, senior product marketing manager at Synopsys, explains how to train the DRAM physical layer using firmware, why that is so important for flexibility, and what kinds of issues engineers encounter when using this approach. » read more

Stream Vs. Pool Data Processing
By Ed Sperling - 08 Apr, 2020 - Comments: 0

Geoff Tate, CEO of Flex Logix, looks at the very different data processing requirements at the edge and in the data center, and what really drives efficiency and speed in applications such as automotive. » read more

Last-Level Cache
By Ed Sperling - 06 Apr, 2020 - Comments: 0

Kurt Shuler, vice president of marketing at Arteris IP, explains how to reduce latency and improve performance with last-level cache in order to avoid sending large amounts of data to external memory, and how to ensure quality of service on a chip by taking into account contention for resources. » read more

PCIe 5.0 Drill-Down
By Ed Sperling - 01 Apr, 2020 - Comments: 0

Suresh Andani, senior director of product marketing for SerDes IP at Rambus, digs into the new PCI Express standard, why it’s so important for data centers, how it compares with previous versions of the standard, and how it will fit into existing and non-von Neumann architectures. » read more

Building A Safety Verification Flow
By Ed Sperling - 24 Mar, 2020 - Comments: 0

Sal Alvarez, senior manager of application engineering at Synopsys, explains how safety verification differs from functional verification, what changes with failure mode effects analysis, and how to determine and verify the effectiveness of safety features. » read more

Enterprise-Class DRAM Reliability
By Ed Sperling - 06 Mar, 2020 - Comments: 0

Brett Murdock, product manager for memory interfaces at Synopsys, examines demand for DDR5 and DDR4 in both on-premise and cloud implementations, what features are available for which versions, how they affect performance and power, how ECC is implemented, and how the data moves throughout these systems. » read more

Improving Circuit Reliability
By Ed Sperling - 03 Mar, 2020 - Comments: 0

Carey Robertson, product marketing director at Mentor, a Siemens Business, examines reliability at advanced and mainstream nodes, particularly in automotive and industrial applications, what’s driving growing concern about the reliability and fidelity of analog circuits, and the impact of running circuits for longer periods of time under different voltage and environmental conditions. » read more

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