Flash Dance For Inspection And Metrology

Chipmakers are moving from planar technology to an assortment of 3D-like architectures, such as 3D NAND and finFETs

For these devices, chipmakers face a multitude of challenges in the fab. But one surprising and oft-forgotten technology is emerging as perhaps the biggest challenge in both logic and memory—process control.

Process control includes metrology and wafer inspection. Metrology is the science of measuring and characterizing tiny structures and materials. Wafer inspection searches for killer defects in chips.

Process control is becoming more complex and expensive at each node. For example, today’s planar NAND flash memory is relatively simple to characterize and inspect, but 3D NAND is not. 3D NAND resembles a skyscraper, in which horizontal levels are stacked and then connected using tiny vertical channels.

“The logical direction was to go to vertical NAND,” said Naga Chandrasekaran, vice president of process R&D at Micron Technology, at a recent event. “But were we ready for vertical NAND? When you look at it from an equipment capability, there were a lot of challenges for vertical NAND.”

Deposition and etch are the most difficult process steps for 3D NAND. “Above all, we have significant metrology challenges today,” Chandrasekaran said. “With some of the technologies we are developing today, the shrink cadence will slow down because we don’t have the right characterization capabilities. Vertical NAND is a solid example of this.”

To solve the inspection/metrology issues for 3D NAND, device makers are throwing a number of tool technologies at the problem. But some technologies simply don’t exist today. So, the question is can the tool vendors respond to the challenges in 3D NAND?

Going vertical
For the foreseeable future, today’s planar NAND will remain the mainstream technology due to cost. Thanks to 193nm immersion and self-aligned double patterning/quadruple patterning, vendors have extended planar NAND down to the 1xnm node. But at that node, vendors are struggling to scale the floating gate.

In fact, 2D NAND will run out of steam at 10nm, prompting the need for 3D NAND. Unlike planar NAND, 3D NAND makes use of vertical stacks or layers to increase the densities. 3D NAND doesn’t require advanced lithography. It relies more on deposition and etch.

So far, Samsung has introduced two so-called V-NAND devices, including 24- and 32-layer chips. In addition, Micron and its 3D NAND partner, Intel, have recently announced a 3D NAND chip.

Today, the big market for 3D NAND is solid-state drives (SSDs) for the enterprise, but the technology is moving into other areas. “We expect solid SSD demand from new models (in the) PC and datacenter,” said Ji Ho Pak, vice president of memory marketing at Samsung, in a recent conference call.

Still, 3D NAND is more difficult to make than previously thought. So, 3D NAND isn’t expected to move into mainstream production until 2017, which is a year or two later than expected. “It’s not a matter of if, but when 3D NAND will happen,” said Dave Hemker, senior vice president and chief technology officer at LAM Research. “In 2015, everybody is clearly increasing the amount of 3D investment and effort. And then, the actual ramp, whether it’s this year or next year, is driven by the situation of a given company.”

Go with the flow
Each vendor has a different 3D NAND process flow. At various steps, the structure goes through a rigorous metrology and inspection flow. The process steps are different than a planar NAND flow. “For a planar device, I just send it to my SEM review tool. It simply takes a top-down picture,” said Brian Trafas, chief marketing officer at KLA-Tencor.

In contrast, 3D NAND is a vertical device, which translates into a multitude of process control challenges. Some of the more difficult metrology steps involve the multi-layer film stack and the high-aspect ratio structures. Finding buried defects is also difficult.

That’s just the tip of the iceberg. In basic terms, the 3D NAND flow starts with a substrate. Then, a chemical vapor deposition (CVD) tool is used to deposit and stack thin films layer by layer on the substrate. This process is much like making a layer cake.

In the metrology flow, the goal is to monitor the film stack deposition process. This, in turn, helps identify the variations beyond the allowed tolerances. “We’re seeing an explosion of process layers. We are also seeing many types of complex film stacks,” Trafas said. “FinFETs, as an example, have multi-layer stacks, but they are very thin. In 3D NAND, we have a multi-layer film stack, which is very thick.”

Often times, optical critical dimension (OCD) metrology tools are used to address the film stack. One OCD technology, spectroscopic ellipsometry, looks at the properties of thin-film structures in finFETs. Ellipsometry is a non-destructive, optical technique.

For the film stack, 3D NAND requires a different type of OCD-like technology–infrared. “When I look at 3D NAND, I need infrared to penetrate deeper into these materials,” Trafas said.

Each 3D NAND vendor uses different materials within their film stacks. “For several film types and use cases, the systems have been extended into the near infrared, particularly for OPOP (oxide and poly stacks), as well as in the replacement conductor loop in the ONO flow for many of the critical tungsten process control steps,” said Kevin Heidrich, senior vice president of applications and strategy at Nanometrics.

One type of infrared technique is called model-based infrared reflectometry (MBIR). In MBIR, infrared light is reflected off a sample. Then, the reflectance intensity is analyzed versus a wavelength with a model of the sample structure.

The knock on MBIR and other OCD techniques is that chipmakers must develop complex and time-consuming models. “Most of them, especially the model-based ones like OCD, thickness and MBIR, need reference data to calibrate,” said Alok Vaid, manager of optical metrology at GlobalFoundries.

One way to obtain reference data is to cut the wafer and do a cross section of the device using a transmission electron microscope (TEM), which can be an expensive process. A TEM transmits a beam through a structure. TEMs are often found in the lab and not in the production line.

Meanwhile, in the 3D NAND flow, the alternating deposition steps are difficult. The next step is perhaps even more challenging. High-aspect ratio trenches, or channels, are etched from the top of the device to the substrate.

To illustrate the complexity of this process, Samsung’s 3D NAND chip has 2.5 million tiny channels in the same device. The aspect ratios range from 40:1 to 60:1. Each one of the tiny trenches or channels must be parallel and uniform within the device, or the chip simply fails.

For the etch and other steps, metrologists use another form of OCD called scatterometry. Scatterometry analyzes changes in the intensity of light in a device. “OCD is used in critical high-aspect ratio etch for the channel hole process, cut mask process, and associated strip back and cleans,” Nanometrics’ Heidrich said.

In addition, metrologists also want to measure the bottom, middle and top portions of these tiny channels. They also want to measure the edge slopes. “You can do a cross section with a TEM, but this is not cost effective,” said Ofer Adan, global product manager at Applied Materials.

Another way of addressing the problem is by using a critical-dimension scanning electron microscope (CD-SEM). The CD-SEM uses a focused beam of electrons to generate signals at the surface of a structure.

Applied Materials, for one, has added new capabilities into the CD-SEM, such as backscattering. A back-scattered electron detector, or BSE, is integrated into a CD-SEM as a means to capture backscattered electrons. This, in turn, enables the CD-SEM to determine the composition or surface topography of a structure.

“If you take our previous model, you would image the backscattered electrons. You would measure them with a secondary electron algorithm,” Adan said. “With our new tool, you can put the energy field very close to the primary energy. And you get much higher-energy electrons, but they come from the surface. They don’t lose energy from the material and you get higher resolution. But you don’t get as many electrons. Still, we’re using the tool’s stability to obtain a good image.”

Meanwhile, after the high-aspect ratio structures are made and characterized, the device undergoes several other complex steps. The end result is a full-fledged 3D NAND device, but then comes the next hard part—defect inspection.

One of the bigger challenges is to find a defect in a multi-layer 3D NAND stack and determine its exact location. Traditional brightfield inspection is one way to find the defect. Brightfield inspection collects light reflected from a defect. In turn, the defect appears dark against a white background.

Still, there are several challenges. “Imagine you have a 24-layer stack device. Eventually, you are going to grow the stack and do some pattern steps to etch through this,” KLA-Tencor’s Trafas said. “My tool has found a defect, but where is it? Sometimes, we don’t have the intelligence to know if it came from the fifth layer or not. It might be at the fifth layer. I may need to take the device to a failure analysis lab and do a cross section with a TEM. You can do that in R&D, but not in production.”

In 2015, vendors are expected to ship 40- and 48-layer devices, which will bring 3D NAND closer to the price-per-bit curve with 2D NAND.

As vendors scale their devices, inspection and metrology will remain challenging. And so will CMP, deposition and etch. “All of those challenges are going to get worse,” Micron’s Chandrasekaran added.