FOPLP Gains Traction in Advanced Semiconductor Packaging

Fan-Out Panel-Level Packaging (FOPLP) for advanced nodes, once hindered by manufacturability and yield challenges, is emerging as a promising solution to meet the industry’s demands for higher integration densities and cost efficiency.

Traditionally, FOPLP has been a go-to solution for cost-sensitive applications in consumer electronics, IoT devices, and mid-tier automotive systems. Its ability to accommodate multiple dies in a compact form factor at reduced cost has made it an ideal choice for integrating mature-node semiconductors.

Panel-level formats can achieve up to 20% to 30% cost savings over fan-out wafer-level packaging for applications requiring high throughput, according to Yole Group.[1] These savings come primarily from the larger usable area on panels, which allows more dies to be processed simultaneously.

In smartphones, FOPLP has been employed for power management ICs, RF modules, and audio amplifiers, particularly for mid-range and entry-level devices. Similarly, early-generation wearables such as fitness trackers leveraged FOPLP for lightweight, thin designs without sacrificing essential functionality. Beyond consumer electronics, FOPLP has seen widespread adoption in IoT edge devices, including smart home sensors and industrial monitors, where scalability and cost-effectiveness are crucial. Automotive applications also have benefited from FOPLP in infotainment systems, connectivity modules, and mid-power electronics, balancing cost efficiency with the reliability demanded by these environments.

“From a device packaging perspective, FOPLP originally was focused on attempting to make relatively low-complexity, low-cost packages even less expensive by processing more units at the same time on large, square panel formats versus standard round 300mm formats,” says Doug Scott, senior vice president of the Wafer Services Business Unit at Amkor Technology. “This has allowed fan-out panel sizes to grow greater than 600mm x 600mm for device packaging. However, as FOPLP becomes more targeted for highly complex, very expensive packages, it could drive panel sizes below 600mm x 600mm due to precise equipment placement/availability and resolution specifications.”

The strengths of FOPLP — cost savings, scalability, and simplified integration — have long positioned it as an effective solution for high-volume manufacturing in applications with less aggressive performance demands. As the industry shifts toward advanced-node packaging, FOPLP is gaining traction as a potential contender. While competing technologies like 2.5D interposers offer compelling performance advantages, their steep costs and technical challenges can limit adoption.

“FOPLP offers potential cost advantages over other approaches by packaging more chips in a large panel format,” explains CheePing Lee, senior technical director at Lam Research. “It provides the flexibility to process panels of various materials and sizes, potentially increasing productivity, increasing yield, and enabling low cost of ownership in high-volume manufacturing environments. However, there are some challenges that can negate the potential cost savings of FOPLP for certain applications, including initial cost of the equipment, a limited supply chain, and processing yield issues due to the large format.”

So while FOPLP brings with it an established process and proven capabilities — offering a more scalable and cost-effective pathway to advanced nodes — the high densities and tighter tolerances at advanced nodes still require solutions to longstanding issues such as warpage, alignment, and process variability. Advancing FOPLP to meet these demands requires substantial investment in new materials, tooling, and methodologies. On the other hand, its lower cost makes FOPLP a uniquely attractive option for bridging the gap between cutting-edge performance and manufacturability at scale.

“The challenges of fan-out packaging lie in managing the complexity of larger die sizes and higher-density designs while ensuring manufacturability and cost efficiency,” said Lihong Cao, senior director at ASE Group, in a recent presentation. “Automation plays a critical role here, as tools like auto-router IC design and auto-generator workflows can reduce design cycle times by half and optimize die placement for better yields, addressing the inherent variability and scalability demands of fan-out processes.”

“Panel-level processes have unique challenges, and specialized equipment is essential to make FOPLP scalable,” says Wenkai Cheng, business development, packaging solutions at Brewer Science. “To meet these needs, equipment providers, suppliers and manufacturers are working closely together to refine equipment for panel-sized applications.”

The push for panels
FOPLP is advancing from its origins in cost-sensitive applications to become a viable option for advanced-node packaging in AI, 5G, and high-performance computing (HPC). This transition is driven by the need for higher integration densities, larger package sizes, and cost-effective manufacturing. However, the technology still faces challenges in material compatibility, yield improvement, and lack of standardization, all of which must be addressed for broader adoption.

Samsung already has made significant progress in deploying FOPLP for advanced nodes. Its Exynos W920 processor, used in wearables, utilizes 5nm EUV technology and FOPLP. TrendForce reported over the summer that Google has adopted Samsung’s FOPLP for its Tensor G4 chips, while companies like AMD and NVIDIA are now working with TSMC and OSAT providers to integrate FOPLP for their next-generation chips. This includes transitioning from wafer-level to panel-level 2.5D packaging, particularly for AI GPUs and multi-die applications, where larger package sizes are critical. Meanwhile, OSATs such as ASE Group and Powertech Technology Inc. (PTI) have expanded FOPLP use to power ICs and RF ICs, addressing cost-sensitive markets.

“AMD is the most aggressive in adopting FOPLP for advanced node chips,” says TrendForce analyst Tom Hsu. “Google is also developing FOPLP with OSATs, but OSATs are still unable to deliver a high enough production yield to make FOPLP economical for legacy nodes.”

TSMC is developing a rectangular substrate measuring 515mm x 510mm for FOPLP, which could triple the usable area compared to traditional 12-inch round wafers, according to a report by Nikkei. While TSMC’s efforts remain in the early stages, CEO Che-Chia Wei acknowledged during a recent earnings call that panel-level fan-out represents a promising path forward. “We are looking at panel-level fan-out technology, but the maturity today is not yet there. Personally, I think it’s at least three years [away]…and we are working on it,” Wei said.

“Innolux and ST Micro, which adopted the FOPLP process package from a licenser, are able to make a profit by FOPLP for legacy nodes,” adds Hsu. “This business model recently emerged in 2023-24, and is likely to expand in the coming years. TrendForce expects FOPLP to become more widespread for advanced nodes from 2026-27 as soon as it is no longer economical for FOWLP to package AI chips with larger die sizes.”

Despite the few early adopters, FOPLP for advanced nodes remains a work in progress. The technology must overcome significant hurdles in achieving uniformity and precision for high-density applications, and die sizes exceeding 10 times the reticle size remain a challenge, with breakthroughs expected only after further investment in materials, tooling, and process innovation. However, with industry heavyweights like Samsung and TSMC investing in its potential, FOPLP is positioned to play a pivotal role in next-generation packaging solutions.

Process innovations
While promising, the transition to FOPLP requires significant investments in new materials, processes and equipment tailored for panel-level manufacturing. These larger panels demand precision in warpage control and material consistency to ensure reliable interconnects across high-density designs.

“Challenges in achieving planarity over large panels remain critical issues,” says Dick Otte, CEO of Promex. “Once you get above a couple of hundred I/O on a package,  you need good planarity. Solder-tipped pillars must be within a few microns of the board pad over the entire surface throughout the reflow process to achieve high yield in all the joints that need to come together.”

In addition, advancements in redistribution layers (RDLs) and the integration of new dielectric materials are critical to improving reliability and reducing power losses in advanced-node designs.

“High resolution copper interconnects require new dry film photoresist chemistry to extend the RDL roadmap from 5µm l/s to 2µm l/s,” says Keith Best, director of product marketing for lithography at Onto Innovation. “The challenge is the aspect ratio required to support the plated RDL structures. For instance, for a 2µm l/s, the photoresist will need to be at least 6µm thick to support the 4µm plating thickness. In addition, the plating uniformity must be within +/-1.5µm of the target thickness across the entire panel to prevent yield loss from RDL bridging. Alternatively, liquid photoresist can be employed using a slit/slot coater to achieve higher-resolution RDL. Both methods require extensive development to ascertain which method will be most suitable for HVM.”

There are other developments, as well. “Recent advancements in materials and equipment for RDL processing in FOPLP have significantly enhanced both cost and performance,” adds Eoin O’Toole, R&D director at Amkor Technology Portugal. “New dry films, including photoresists and dielectrics, now support a broader range of dimensions, with gains in electrical performance and compatibility with thick metal layers. On the equipment side, plasma processing platforms are now capable of handling larger panels, and the increasing availability of panel-capable LDI systems is reducing exposure costs. Additionally, cluster equipment and advanced lamination systems are improving efficiency and enabling the application of dry films, even on uneven surfaces.”

One of the pivotal enablers of FOPLP’s transition is to temporarily bond known good dies to the carrier panel during the initial stages of the packaging process, preventing die shift before the final mold encapsulation step. Advanced adhesives now offer higher thermal stability, closer CTE (coefficient of thermal expansion) matching, and improved adhesion.

“Materials with low coefficients of thermal expansion have been instrumental in addressing thermal mismatch and minimizing warpage,” says O’Toole. “New liquid and granular mold compounds are available with potential gains in reliability performance.”

Additionally, reinforcing layers and thermosetting polymers have improved panel flatness, ensuring better alignment during processing.

“Process uniformity of metal deposition, plating, and etch needs to be consistent over a non-round large-panel format versus a proven round 300mm format,” says Amkor’s Scott. “Panel pre-processing and post-processing also need to be defined, depending on the specific FOPLP processing steps.”

Lack of standards slow adoption
Despite the promising advancements in fan-out panels, the road to full adoption for advanced nodes is not without significant hurdles. Scaling FOPLP to panel size has amplified mechanical challenges, particularly warpage and alignment issues. Even minor misalignments can result in defects that compromise yield and reliability. In addition, achieving consistent process uniformity across these large and often irregularly shaped panels requires precision tooling and advanced materials specifically tailored to panel-level applications.

“Electroplating across a large panel uniformly is one of the most challenging process steps,” says Lam Research’s Lee. “Full panel uniformity is difficult due to size, shape, and warpage of the panel, and if not achieved, may lead to topography issues on subsequent layers.”

A persistent barrier to FOPLP’s broader adoption is the lack of a standard panel size. Unlike wafer-level packaging, where 200mm and 300mm standards dominate, panel dimensions vary widely across manufacturers, creating inconsistencies in tooling and equipment design. Custom solutions must often be developed for each unique panel size.

“In wafer-level packaging, we’ve converged on standard sizes,” said ASE’s Cao. “But for panels, the lack of standardization means manufacturers must adapt their equipment to accommodate different dimensions. This adds cost and complexity to the design process.”

“One of the biggest challenges with panels is the lack of standardization in size, which dictates a huge part of the system design,” says John Hoffman, computer vision engineering manager at Nordson Test & Inspection. “With wafers, we’ve got 200mm and 300mm standards, but panels vary widely. This variation complicates system design, particularly in handling and flattening warped panels. On wafers, a vacuum chuck ensures flatness, but for panels, terrain-following capabilities are often needed to account for undulations.”

The introduction of SEMI’s 3D20 standards is a step toward addressing this issue. These specifications provide a framework for panel characteristics, enabling equipment providers to design tools that are compatible with standardized panel sizes, reducing costly customizations. However, widespread adoption of these standards is still in its infancy, and panel dimensions today range from 650mm x 650mm to 400mm x 500mm, posing ongoing challenges for equipment vendors.

“Scaling for FOPLP is cost prohibitive if high line utilization cannot be achieved,” adds Amkor’s  Scott. “Since a large portion of FOPLP lines are not fungible with standard 300mm processing, open capacity leads to return on investment concerns. FOPLP is an ideal solution if the line can run with high utilization since initial investment to scale FOPLP could be greater than $100 million or $200 million.”

Bridging design and manufacturing gaps
From a design perspective, FOPLP introduces complexities that straddle traditional methodologies for silicon interposers and PCB-like substrates. Bridging these distinct approaches demands new tools and collaborative frameworks to address the unique demands of fan-out packaging.

“The shift to FOPLP represents an exciting evolution, but it also requires bridging two distinct methodologies,” says Shawn Nikoukary, senior director of solution services at Synopsys. “Substrate designs traditionally use PCB-like tools, while silicon interposers depend on chip design tools and sign-off processes. Fan-out packaging introduces features from both worlds, creating a gray area that demands new tools and approaches.”

EDA advances are playing a crucial role in managing these challenges. AI-driven solutions are helping optimize design configurations by navigating the exponential complexity of multi-die systems, balancing thermal and electrical tradeoffs, and enabling iterative prototyping.

“The complexity of advanced packaging is pushing the boundaries of design space optimization,” says Keith Lanier, director of product management at Synopsys. “With the size of the dies, the number of interconnects, and the need for thermal and electrical tradeoffs, we are seeing a growing reliance on AI-driven solutions. These tools help manage the exponential design space and enable iterative exploration of configurations to optimize both performance and manufacturability.”

However, these tools must also integrate with co-design platforms that align system-level performance with advanced FOPLP requirements. Collaboration between design and test teams is essential to ensure that the final product meets performance and manufacturability standards.

“Comprehensive co-design platforms are essential for aligning system-level performance with advanced FOPLP requirements,” adds Nikoukary. “Early exploration and the ability to prototype early technology decisions is absolutely critical, especially in addressing thermal hotspots and EMIR.”

A collaboration mandate
The challenges of advanced packaging technologies like FOPLP cannot be addressed in silos. Collaboration across the ecosystem—spanning material suppliers, equipment vendors, OSATs, and system integrators—is critical to overcoming technological, economic, and logistical barriers.

“Partnerships with customers and suppliers are vital to addressing issues like process uniformity, warpage, and alignment in FOPLP,” says Onto’s Best. “By working together, we’ve been able to refine our advanced lithography systems to meet the evolving needs of the industry.”

Others agree. “Effective collaboration across the ecosystem requires clear communication and a shared understanding of technological needs and limitations,” says Promex’s Otte. “The biggest issue is that nobody fully understands all the options and what they imply. Better communication, especially across international lines, is critical to achieving progress. Verbal or written explanations should always be supported by drawings, photos or some other visual method. ”

This is easier said than done, however. “At a fundamental level, there’s a significant divide between the environments in which substrate and PCB engineers work versus traditional chip designers,” explains Nikoukary. “Substrate and PCB teams typically operate in Windows environments and use tools designed for package and PCB simulations, while chip designers are entrenched in Linux and need chip design and sign-off simulation tools. Bridging this gap has been challenging, particularly when training substrate engineers to adapt to brand new tools, methodologies, and the Linux-based tools required for advanced packaging.”

The differences go beyond just software environments. “There’s also a disconnect in how design rules are defined and applied,” Synopsys’ Lanier says. “Silicon foundries and packaging companies approach design rules in fundamentally different ways. While some standards exist, we still need better alignment to ensure these rules meet the demands of emerging designs and enable seamless integration across domains.”

Conclusion
Fan-out panel-level packaging is poised to play a transformative role in the future of advanced semiconductor packaging. As technologies like AI, 5G, and high-performance computing demand greater integration densities and cost efficiency, FOPLP offers a scalable, cost-effective alternative to traditional wafer-level packaging. However, widespread adoption hinges on overcoming challenges such as warpage, alignment, and process uniformity across large panels.

Standardization and collaboration will be pivotal to the future success of FOPLP. Currently, the lack of consistent panel sizes and design rules across the industry increases complexity and cost. Efforts like SEMI 3D20 aim to address these gaps, providing specifications for panel characteristics and enabling broader equipment compatibility. At the same time, deeper collaboration between OSATs, material suppliers, and EDA tool vendors is critical to refining co-design platforms, improving manufacturability, and reducing development timelines.

Looking ahead, FOPLP is expected to expand its role in chiplet-based designs, offering cost and performance benefits for multi-die systems in high-volume applications. With continued innovation in materials, equipment, and process methodologies, FOPLP is well-positioned to bridge the gap between cutting-edge performance and manufacturability. As industry stakeholders align on standards and accelerate partnerships, FOPLP could become a cornerstone of next-generation packaging.

—Laura Peters contributed to this report.

Reference:

1. Pereira, G. (2024). Fan-out packaging reaching new heights: Market and technology overview. Paper presented at the IEEE 74th Electronic Components and Technology Conference (ECTC), Orlando, FL, September 9–11, 2024. IEEE.

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