MEMS: Improving Cost And Yield

MEMS devices inspire awe on the design side. On the test and manufacturing side, they evoke a different kind of reaction.

These are, after all, the intersection of mechanical and electrical engineering—a joining of two miniature worlds that are the basis of some of the most complex technology on the planet. But getting these devices to yield sufficiently, understanding what does or does not work, and figuring out how to do this with the kind of economies of scale that have made semiconductors affordable present some monumental challenges in the MEMS world.

There are several reasons for this:

• chips are like black boxes. In fact, they often are hermetically sealed because many of these devices need to work in a vacuum. That makes testing much more difficult.
• Yield depends on other factors than just the MEMS device. Frequently these chips are packaged with other chips. Some are heat and pressure sensitive, and because it’s difficult to test these devices there is no simple way to determine reliability.
• The competition for many of these devices is too high to warrant more investment, but the process of creating these chips can be slow and expensive. That disconnect limits innovation both in the process and in the MEMS devices themselves.

Processes generally are well developed for accelerometers, gyroscopes and capacitive pressure sensors—the inertial sensors that represent the highest volume of the MEMS market. But that process is restrictive. Because of ROI, manufacturers are reluctant to change it once it is established. And even then, there are no guarantees these devices will work when they are combined in packages with other sensors.

Fig. 1: MEMS chip. Source: Applied Materials

“Yield is an issue, especially at the beginning,” said Babak Jamshidi, deputy director of product technology marketing at STATS ChipPAC. “We have to establish a process and a set of specifications for a specific package type. Smaller customers could be defining something entirely new, so there might be yield loss there.”

This is particularly true in new application areas for MEMS, where volume is lower but profits are potentially higher. The MEMS market is split between the highly commoditized inertial sensors and other types of devices that rely on a mix of advanced materials, such as piezoelectric substrates and RF-SOI. (See MEMS: A Tale Of Two Tough Markets.)

“This is all very fragmented,” said Jamshidi. “But now we are going through the era of IoT, where there is a need for multiple sensors by everyone. There is an explosion in volume, which is a multiplier for capacity investments. There also is a new trend where the design starts are not at the IDM but at the fabless companies. The IDMs will continue to develop chips, but the market is reaching the point where even established players are starting to outsource some of the technologies, which is opening up capacity for more profitable chips.”

Economies of packaging
One of the emerging solutions for improving profitability involves new packaging schemes. Today, the majority of MEMS sensors are encapsulated in a polymer-based molding compound, which is used to protect them. There are other options available, including pre-molds and low-cost quad flat no-lead (QFN) packages, which improve the economics for MEMS devices, but with some limitations.

“The entry point today for those is quite low, and we can use equipment we have today for the test market,” said Christophe Zinck, senior application engineering manager at ASE. “We are seeing an increase in chips with more functionality, but the pre-mold puts a limit on how much functionality you can add into components. By using a QFN package you can keep the same footprint, add more functionality, and not shrink the devices.”

Fan-out wafer-level packaging (FO-WLP), is another option being proposed to increase functionality in a given footprint without significantly increasing the price. “Right now it costs more because it is a niche market,” said Zinck. “But with inertial sensors, you cannot thin the MEMS as much as you want. To go below 0.6mm for the total package is very difficult.”

Different packaging is available for different applications. But because the MEMS market is so fragmented, it’s not clear which of those approaches will become mainstream or how pricing will be scaled.

“Fan-out wafer-level packaging or flip chips have taken a back seat because of bumping, but you can replace the bumps and achieve thinner devices,” said STATS’ Jamshidi. “You won’t see all devices moving to FO-WLP. With microphones, the membrane requires a very custom package. But inertial sensors can use the process already put in place for FO-WLP.”

Fig. 2: Fan-in (a) and fan-out (b) wafer-level packaging. Source: STATS ChipPAC.

FO-WLP could play a significant role in sensor fusion because it allows multiple devices to be connected almost like LEGO blocks on a substrate.

Test strategies
Ensuring that MEMS chips will work isn’t straightforward, however, and it gets more difficult as new packaging approaches are utilized.

“Test happens on two fronts for a sensor, before the seal and at the wafer-level measurement,” said Joey Tun, principal market development manager at National Instruments. “So you may measure capacitance if the MEMS device is a variable capacitor. Or you may have a package with everything in there, including signal conditioning and a local MCU.”

Fan-out wafer-level packaging requires testing the MEMS chip to make sure it’s a known good die before it is packaged. In addition, wafers need to be tested before and after they are “reconstituted.” This is critical because in some cases, different vendors supply the wafers and the MEMS devices.

The challenge is making sure that the testing process doesn’t cause problems. Too much testing can damage sensitive parts. Too little testing, particularly of such effects as bias temperature instability, can allow unreliable parts to escape into the market. BTI is particularly problematic, and negative BTI is worse. As devices shrink, the threshold voltage shifts with applied stress. In the case of automotive applications that stress comes in the form of testing, which can be done at temperatures as high as 300° C.

“With automotive, which is about 40% of MEMS devices, the degree of test requirements is higher,” Tun said. “This is the harshest environment, and the testing needs to be more intensive. Testing is typically for reliability on CMOS for a given process node over a given lifetime under normal operating conditions. But with shrinking geometries, the lifetime is uncomfortably close to the end device.”

Testing also is different for a closed device than one that is accessible. At the wafer level, for example, the primary consideration is yield.

“The quality and yield of MEMS devices is assessed at the foundry using wafer-level electrical testing,” said Jin Siew Lim, MEMS product manager for GlobalFoundries‘ Singapore Fab. “Although predicting yield of packaged parts by using wafer-level tests is challenging, wafer-level tests have been developed to the point where they can predict the package-level yield with a very high degree of confidence. Reliability assessments are carried out to test the hermetic sealing of MEMS devices at the package level.”

That’s an important piece of it. But there are other steps, too. Predictive analysis also is used on the design side, while output tests are used once a device has been packaged.

“You can predict thermal behavior in response to temperature fluctuations,” said Stephen Breit, vice president of engineering at Coventor. “So there may be different thermal coefficients of expansion for the package. The package can warp, which affects MEMS output. You can sense those changes, by measuring the output from a sensor. If you have done a good job with the design and simulation, you can measure the output without actually seeing the chip. This is especially important because some of these devices don’t work without the package.”

Sometimes they don’t work with the package. Mike Rosa, director of technical marketing at Applied Materials, described one case where a company deposited aluminum on CMOS to create contact pads, and germanium on the MEMS device, and then bonded them together.

“In that bond they did a vacuum seal, and they also made electrical contact between the MEMS and the CMOS,” he said. “The problem was that you had 410° C with 60-plus kilo-newtons of force across an 8-inch wafer. At the die level, you had suspended MEMS structures. If you added mechanical stress, it changed the mechanical dynamic range of the MEMS device. That caused a big issue. It wasn’t packaging by itself. It was the way they bonded these wafers.”

Manufacturing considerations
Manufacturing of MEMS chips adds its own set of issues. Because of the downward pressure on average selling prices, many of the MEMS foundries utilize older technologies, where the up-front capital expense investments are lower. But the real economies of scale come from the new manufacturing processes and capabilities. Foundries generally weigh how much return they can expect from those kinds of investments, just as they do with other CMOS chips.

“The same concept applies to whether it makes sense to putting the investment into 300mm fab,” said Yan Qu, senior regional marketing manager at UMC. “Inertial sensors, microphones and bulk acoustic wave devices are responsible for more than $1 billion of the MEMS market, according to IHS, but it comes down to how much volume you can potentially get before putting down the investment.”

For the most part, MEMS chips are manufactured at 200mm today using fan-in approaches, primarily because the number of I/O connections is not that large with a MEMS device. Using that approach, the bumping is directly under the device. This is significantly different from a DSP, for example, which may have hundreds of I/Os, said Applied Materials’ Rosa.

Where that becomes problematic is when devices shrink, such as a thinner phone, which in turn requires a smaller footprint to accommodate the new form factor.

“In the past, you’d make your wafer on a wafer, then there was another wafer that had all these cavities and you’d cap one wafer and you’d end up with a sandwich, dice it off, and you were done,” he said. “Where that standard packaging approach starts to become ‘advanced’ is when smartphones or other devices require a reduced form factor. Then you start going from a 1mm-high piece of silicon down to maybe 200 to 250 microns. You then grind the wafers and thin them. The tricky thing with MEMS is that you can reduce the CMOS footprint, but the MEMS doesn’t shrink. With gyros and other sensors, you need a certain amount of mass to sense the motion. There’s a lot of ‘advanced packaging schemes’ that involve the CMOS made on one wafer, the MEMS on another, some fancy integration of the two using wafer bonding. And then, depending on the complexity, you might have TSVs in there, as well.”

Conclusion
Demand for MEMS devices is forecast to grow significantly over the next few years, particularly as more sensors are required for devices that are either in motion or used to sense motion. This includes everything from cars to robots to electronic sniffers and ultrasonic fingerprint sensors.

Some of these devices are produced in volume. Some are customized. And some are a bit of both. But the manufacturing and testing challenges aren’t getting easier, particularly as system vendors demand more reliability, smaller packages, and all for less money than they paid in the past. This remains a very tough market, and it’s only going to get tougher because the innovation demanded to meet these goals costs money, both in terms of up-front investments and equipment.

Whether that results in more outsourcing, more standardization, or utilizing alternative, less expensive ways to sense the physical world remains to be seen. Changes are coming to this market. But what they will look like, when they will occur, and who ultimately will benefit from those changes is unknown at this point.

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