More Lithography/Mask Challenges (Part 2)

Semiconductor Engineering sat down to discuss lithography and photomask technologies with Gregory McIntyre, director of the Advanced Patterning Department at Imec; Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries; Regina Freed, managing director of patterning technology at Applied Materials; Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To view part one of this discussion, click here.

SE: Besides today’s extreme ultraviolet (EUV) lithography, the industry is also developing next-generation EUV. This is known as high numerical aperture EUV or high NA EUV. Why do we need high NA EUV?

McIntyre: It’s pretty much for all the same reasons that we want to go to EUV, compared to immersion. With immersion today, you are talking about three, four or five exposures or more. That gets very expensive and complicated. There is a lot of processing required. Going to EUV, you go back to a single exposure solution. That simplifies the process quite dramatically, reduces the cycle times and overall costs. At some point, in the next node or two or three, we will start using multi-patterning. We need to use EUV with multi-patterning. At the same point, you have the same exact argument. Then, high NA starts to become attractive. Going to a tool that has a higher resolution ends up allowing you to reduce the mask count and reduce the process complexity.

Fig. 1: Today’s EUV optics (NA 0.33) versus high NA EUV optics (NA 0.55) Source: ASML

SE: What are the challenges with high NA EUV?

McIntyre: You still have stochastics effects to worry about. Your feature sizes get smaller, so the impact actually goes up for a constant dose value. With the high NA tools, you are talking about using a 500-watt or a 1-kilowatt power source. You do need your power to go up. Getting to a high NA tool that you can realize has a lot of challenges. One of them, of course, is getting the high power source.

Hayashi: My concern is the mask side. High NA uses an anamorphic technology. Someday we will need to look at a new absorber material for the mask in high NA. To reduce the mask 3D effects, we need a thinner effective absorber for that generation. That will be a completely different material. That creates the next challenges for mask making, like deposition, etching, repair and cleaning. That’s one of our concerns.

McIntyre: Maybe to follow-up on the alternative absorbers, one of the big challenges is that the majority of the materials that people are looking at are great for imaging. They are thinner and higher-absorbing, but they are very difficult to pattern. So you need to figure out how you are going to etch these. Typically, they don’t work with a dry etching process. They are very difficult to repair with an e-beam type repair tool. So getting to a process of how you can actually do this is going to be difficult. And once you do that, then getting to a tool-set that you can bring to the mask house to implement those processes offers another big challenge. But if you can do it, the benefits you get for imaging are quite significant.

SE: What about EUV with double patterning?

McIntyre: Eventually, you might have to do EUV double patterning. You can’t make the spaces any smaller because of the stochastic challenges. Then, it is more cost effective to go to a bigger feature, but use two masks and go a lower dose value. Maybe that ends up being a more cost-effective solution.

SE: Some chipmakers initially will insert today’s EUV lithography at 7nm. Still others will use today’s 193nm immersion with multiple patterning at 7nm. What are the challenges in terms of extending immersion/multi-patterning to 7nm?

Levinson: The complexity essentially goes up geometrically in the world of multiple patterning. So if you have double patterning, you have twice the complications. When you go to triple patterning, it’s more like four or eight times the problem. The problem just increases. Some people are concerned about doing cuts. That becomes very challenging and it’s very hard. In theory, all you are going to do with multiple patterning—say triple patterning and quadruple patterning—is to do what you did in double patterning. You just do it more times. But it’s a geometric increase in complexity that makes it so non-trivial. That’s why we want EUV.

Hayashi: For extending multiple patterning, most of the problem is overlay accuracy. Then, in the mask equation, the customer’s requirement for the mask-set for certain layers is very critical. It’s almost at the limit of the capabilities of the current mask writers. I hope multi-beam mask writers will improve the image placement accuracy. There is less noise with these systems, so the image placement will be better.

Fujimura: Multi-beam is reporting good image placement accuracy, so that will certainly help with multiple patterning. However, the industry consensus seems to be that there’s an economic limit to the feasibility of the workaround using more multiple patterning. Therefore, EUV has to be the answer. The industry is saying that EUV will start in production at 7nm, at least for limited use. But there seems to be an increased general perception that shot noise will soon be an issue with EUV. EUV will probably see multiple patterning soon, as well.

McIntyre: The back-end-of-the-line and middle-of-line tend to be the most aggressive from a pitch scaling, patterning perspective. That seems to be getting even more challenging. We can pattern the front-end dimensions. But getting to smaller gate lengths and less fins creates a lot of electrical issues in devices. What you are seeing happen is that the front-end is starting to slow down. Thus, to compensate for it, people are trying to super-scale the backend and go even further down in pitch. That creates a lot of challenges for patterning. It creates challenges for metallization. When you get to these very small metal lines, you now have to get down, connect and form contacts. Even in EUV, we will have to use self-aligned schemes in order to keep our EPE under control.

SE: Let’s move to other patterning approaches like self-aligned processes. These approaches enable technologies like self-aligned double/quadruple patterning (SADP/SAQP). Using this approach, chipmakers have been able to scale their devices to the next nodes. Now, with new materials, the industry is evolving these self-aligned approaches for the next wave of processes and structures. What’s next?

Freed: There are lots of different flavors of it. It’s independent of the patterning technique. At some point, the errors become so big and you’re struggling. So we are trying to help the industry to overcome these challenges. Imec is looking at what it calls scaling boosters like fully self-aligned types of technologies. IBM has made presentations on some of them. Others have made presentations on them. The concepts are all very similar. To accomplish this, you use materials and materials selectivity to align a feature. So, you build up a sequence of materials by either recessing them or using gap fill with CMP and selective removal. And then you use that as a guiding structure. Or maybe you build them from the bottoms up with some selective processes.

SE: How does that solve the problem?

Freed: We are dealing with cycle times. We are dealing with multiple patterning. The fact is there are challenges on how to align all of these processes. By making material systems that align these processes, we take that problem away and then we simplify the patterning. We still have to do a lot of patterning steps, but at the end, we have a device that yields. Self-aligned gate contacts are a good example of that. Via landing is another one. So people are looking at different ways to align vias. For this, you have seen presentations on multi-color patterning, where people use spacers and gap fill to separate features from each other.

SE: What’s happening in nanoimprint lithography?

Hayashi: Nanoimprint is currently being targeted for memory devices. Hopefully, that’s early next year. We are trying to reduce the feature size for the nanoimprint template. Our people have presented papers about resolution improvement down to 14nm lines and spaces with a multi-beam mask writer. Multi-beam uses low-sensitivity resists. We can get a good signal-to-noise. Then, the scatter error is quite small.

Fig. 2: Nanoimprint process vs. traditional optical lithography. Source: Canon

SE: What are the main apps for nanoimprint?

Hayashi: We think this technology is good for current memory and also next-generation memory like cross-point. Nanoimprint has no pattern field limit. If people want to make a larger chip with one shot, they can do it. The line-edge roughness is quite small. For nanoimprint, there is no additional error source for patterning. Those are the benefits.

Fujimura: It is not dependent on the number of photons.

Hayashi: Currently, it’s targeted for 3D NAND in the near term. They need good uniformity, pattern fidelity and dense hole arrays.

Fujimura: Nanoimprint is still used for defect tolerant applications.

Hayashi: The defect density is most of the problem in nanoimprint. It’s close to the NAND requirements, but far from immersion.

Levinson: The defect density is far from what we do in logic. So we will watch as our colleagues in memory work on nanoimprint technology. If there is an improvement seen, we can take a look at it. But we are so busy now with EUV.

SE: Another futuristic patterning technology is selective deposition. Using atomic layer deposition (ALD) tools, selective deposition involves a process of depositing materials and films in exact places. What’s happening with selective deposition or other selective processes?

Freed: Selective processing has been used in the fab quite a while. Epi is a perfect example of a selective process. What is important here is surface chemistry, how to make the surface clean and the growth conditions. In addition, there is selective removal. It’s not just atomic layer etch. It’s a chemically-selective process. Removal processes are making a lot of progress. They are being used for silicon germanium, 3D NAND and other structures. In selective deposition, it’s a little slower. But we see some paths forward in making that happen, based on our experience from the things that we’ve learned from epi and other selective processes that we’ve done before.

Fig. 3: Area-selective deposition. Source: Eindhoven University of Technology, Atomic Limits

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