Next EUV Issue: Mask 3D Effects

As extreme ultraviolet (EUV) lithography moves closer to production, the industry is paying more attention to a problematic phenomenon called mask 3D effects.

Mask 3D effects involve the photomask for EUV. In simple terms, a chipmaker designs an IC, which is translated from a file format into a photomask. The mask is a master template for a given IC design. It is placed in a lithography scanner, which projects light through the mask. That, in turn, is used to pattern images on a wafer.

For EUV, the mask is a multi-layer structure with absorbers. Based on tantalum (Ta) materials, each absorber consists of a 3D-like feature that juts out on top of the mask. In operation, EUV light hits the mask at a 6-degree angle, with the reflections potentially causing a shadowing effect or photomask-induced imaging aberrations on the wafer. This issue, known as mask 3D effects, can result in unwanted feature-size dependent focus and pattern placement shifts. In addition, there can be large differences in focus between 1D and 2D features, which limits the yield process windows, according to experts.

Fig. 1: Cross-section of an EUV mask. In EUV, light hits the mask at an angle of 6°, resulting in mask 3D 3D effects. Source: Imec, KU Leuven, Ghent University, PTB

The industry has known about the problem for years, but it hasn’t been a top priority. For one thing, the industry has been pre-occupied with the other challenges in EUV, namely the power source. In addition, EUV processes can cause problematic random variations, also known as stochastic effects. These effects, in turn, cause stochastic-induced defects in chips.

Now, mask 3D effects are entering the radar screen. These effects are not new and occur in today’s complex optical masks. But they are problematic for EUV, and become worse at each node. “There are these mask 3D effects that cause pattern placement errors,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries. “The fortunate thing is that at 7nm, the problems are not too bad. But they get much worse as we try to shrink, particularly for mask 3D effects.”

Mask 3D effects are here to stay with EUV, at least to one degree or another, depending on the situation. For some time, though, the industry has been looking at ways to mitigate the problem. Among them are:

• Use computational lithography to correct the problem.
• Develop thinner Ta-based absorbers to reduce the problem on the EUV mask.
• Replace Ta with new absorber materials, although this presents several challenges.
• Develop new multi-layer EUV mask materials.
• Move to high-NA EUV.

Making EUV masks
GlobalFoundries, Intel, Samsung and TSMC hope to insert EUV lithography at 7nm and/or 5nm. Chipmakers need EUV because it’s becoming more difficult to pattern the critical features in chips.

ASML, meanwhile, is shipping its first production EUV scanner. In EUV, a power source converts plasma into photons at 13.5nm wavelengths. Then the light bounces off a scheme of 10 reflective mirrors. At that point, the light hits the mask and moves toward the wafer.

Fig. 2: Accurately bouncing light. Source: ASML/Carl Zeiss SMT Gmbh

The mask is one of the key components in EUV. The goal is to develop defect-free masks. If the mask has a defect, the irregularities might get printed on the wafer, so it’s important to capture mask defects. But that’s not always easy.

Additionally, chipmakers want a pellicle to protect the EUV mask during operation, although this technology is still in R&D. The pellicle is a thin membrane, which is placed on top of the mask to protect it from dust or particles.

Meanwhile, in mask making, the process starts with a mask blank. Made by a mask blank vendor, the blank serves as the base structure of a mask. Today’s optical mask blanks consist of an opaque layer of chrome on a quartz substrate.

Fig. 3: Fabrication of EUV mask. Source: Sematech

In comparison, an EUV mask blank consists of 40 to 50 alternating layers of silicon and molybdenum on a substrate, resulting in a multi-layer stack that is 250nm to 350nm thick. These materials are used to help reflect EUV light at 13.5nm wavelengths.

For the multi-layer stack, the challenge is to deposit precise layers with no defects. The goal is to focus “on thickness control of the multi-layer to improve reflectivity that will directly translate to sharper imaging of the features at the EUV scanner,” said Sandeep Kohli, a principal research scientist at Veeco.

On top of this multi-layer stack, the mask blank also includes a ruthenium-based capping layer, followed by a Ta absorber.

In the production process, though, the mask blank is prone to defects. But over time, the industry has reduced the defect levels to the single-digit level.

Generally, the industry has ironed out the bugs. “The current EUV mask blank process took almost a decade of collaborative industry-wide development before reaching its current level of maturity. Many years of effort went into learning how to create defect-free blanks with the required flatness, how to deposit multi-layer films with acceptable embedded defect levels, and how to create an absorber stack that meets all end use requirements,” said Moshe Preil, senior product marketing manager at KLA-Tencor.

Once the mask blank meets spec, it is shipped to the photomask vendor in a separate facility. At this point, the photomask is made.

Initially, the mask blank is patterned using an e-beam mask writer, based on a given chip design. Then, an etch tool etches portions of the Ta absorber layer. Typically, the Ta absorber layer is 60nm thick. The remaining absorber is coated with an anti-reflective material.

As stated above, the mask blank might have buried defects. Mask makers must find a way to prevent those unwanted defects from showing up on the photomask. To solve the problem, the defect is covered by the absorber. All told, the etched portion of the mask reflects EUV light, which, in turn, is used to pattern the features on a wafer. The absorber absorbs EUV light.

Fig. 4: EUV mask. Source: GlobalFoundries

Then, the EUV mask is inspected and then shipped to the fab, where it is placed in an EUV scanner for patterning a feature on a wafer.

Dealing with mask 3D effects
Meanwhile, in a scanner, EUV light hits the mask at a 6-degree angle or chief-ray incidence angle. In simple terms, EUV light is projected at an angle to prevent the overlap of incident and reflected light.

From there, light goes through the mask. Diffraction orders are formed. Some orders make it through a scanner slit, which are then collected by a lens, and eventually the images reach the wafer.

The topology of the EUV mask, coupled by the angle of light, causes a shadowing or mask 3D effects. “One typical EUV effect is mask shadowing,” said Gandharv Bhatara, product marketing manager at Mentor, a Siemens Business. “Mask shadowing effect is the consequence of the EUV mask absorber height and the non-telecentric illumination at mask level, which modulates the captured intensity from the shadowed mask area through the reflective optics onto the wafer. At the wafer level, this causes a differential horizontal–vertical CD bias and image shift which is slit-position dependent.”

So what’s the solution? There are several ways to mitigate these shadowing and mask 3D effects—computational lithography, new mask materials, and high-NA EUV.

In simple terms, computational lithography uses computations to optimize a given process. For example, it can be used to optimize the mask, sometimes called source-mask optimization.

It also can be used to simulate and model mask 3D effects. Then, the effects can be corrected using optical proximity correction (OPC) on the mask. OPC makes use of tiny shapes, or sub-resolution assist features (SRAFs). The SRAFs are placed on the mask, which modifies the mask patterns to improve the printability on the wafer.

“We face 3D mask effects in EUV that are very similar to DUV. The diffraction at the photomask causes phase effects, which lead to very similar effects in wafer printing as the aberrations of projection optics. We manage these effects in much the same way, using OPC, assist features and source-mask optimization,” said Michael Lercel, director of product marketing at ASML.

Computational lithography solves some but not all issues, especially as the industry moves from 7nm to 5nm. “It’s a complexity problem. When we go to the OPC engineers, we say: ‘You have to get good linewidth control across the focus and dose, just like you did in optical lithography.’ But now, you also have to worry about pattern placement. You also have to worry about the fact that features have different planes of best focus with the types of illumination that we’ve used in the past. And the solution to bring everything into focus and keep it all in the same place may be different for different features,” GlobalFoundries’ Levinson said.

In a recent paper, GlobalFoundries demonstrated the ability to correct aberrations with the right choice of illumination conditions. “But it was a very small number of features. The aberrations were on one tool. With multiple tools, there are many, many types of features. I am not sure how easy it is to solve,” Levinson said.

There are other challenges. “Mask 3D effects are a significant issue for OPC/ILT for optical masks already. It would be fair to say that a leading-edge wafer lithography simulation solution–whether OPC/ILT or verification–is not complete without incorporating mask 3D effects. This has been a computational challenge to strike the right balance between runtime and accuracy,” said Aki Fujimura, chief executive of D2S. “With EUV, the problem adds another complexity in that the reflective masks require a 6-degree incident angle. This offsets the pattern placement in a way that is dependent on that feature’s location. Correcting for this requires shifting the pattern on the mask differently for each location of a pattern, even if the same pattern is being printed repeatedly. Printing 12 identical chips on the wafer requires 12 different corrections.”

This impacts the data processing times in mask production, which subsequently plays a role in mask turnaround times in the industry.

Today, data processing times are increasing with traditional complex optical masks. “EUV makes this worse by first requiring higher resolution in any simulation-based processing of data. On top of that bad situation, the incident angle issue requires OPC/ILT and all data handling after that to process the entire reticle. We can’t process the chip once and then just step and repeat it in a job deck when writing the mask,” Fujimura said.

Summarizing the situation, Gregory McIntyre, director of the Advanced Patterning Department at Imec, said: “3D mask effects are essentially just that. They are feature-specific aberrations. Computational lithography, OPC and that stuff can bias the mask size. That changes the amplitude, but it doesn’t affect the phase. These are all phase effects that are caused by light propagating through the thick absorber. It’s not so straightforward.”

New mask materials
Another solution is to re-engineer the mask. As stated above, EUV masks are multi-layer reflectors, which consist of alternating layers of silicon and molybdenum. The Ta absorber is 60nm thick.

Today’s EUV masks are suitable for 7nm. For 5nm, though, the EUV mask requires a slight change. “Moving into 5nm, or to and through 5nm, the mask 3D effects will become more and more important. So shrinking the absorber stack is the way to address that,” said Mike Green, a researcher at Photronics.

At 5nm, the roadmap calls for a thinner Ta absorber layer at 55nm. This will improve the imaging quality, but it won’t solve all mask 3D effects.

There is another issue, too. A Ta-based absorber reaches the limit at thicknesses of 55nm, according to experts. “Alternate materials are needed to go to any thinner than 55nm,” Green said.

Fig. 5: Optimizing the blank material Source: Photronics

For some time, the industry has been exploring the idea of replacing Ta with a new material. Cobalt (Co), nickel (Ni) and various alloys are candidates, but they present some challenges, namely they are difficult to etch. So the industry may need new tools for a material change in the mask infrastructure. In the short term, though, this seems rather unlikely, as most mask makers are unwilling to invest in new tools or don’t have the funds.

Still, there is some promising work in R&D. Ideally, the goal is to find a new absorber material with the right refractive index. The refractive index describes how light propagates through a material.

For EUV, the light will undergo some attenuation. To account for this, the industry uses a complex refractive index metric. For this, the formula is: n = n + ik. (The number “n” is the refractive index. It also indicates the phase velocity. “k” is the imaging part and the extinction coefficient.)

“To reduce mask absorber height-dependent (mask 3D) effects, a material that absorbs more EUV and has higher ‘k’ than Ta is necessary,” said Vu Luong, a researcher at Imec, in a recent paper. “A material with ‘n’ close to unity is preferred.”

Ni is the ideal material to replace Ta, but it sometimes forms unwanted grains, according to Imec. To solve the problem, researchers combined Ni with aluminum (Al), forming a Ni-AI alloy.

In the lab, a 39nm Ni3Al alloy demonstrated promising imaging results. But the transition from Ta to Ni-Al or other types of absorbers may take several years.

“Any changes to the established process will take years to develop, optimize and validate before being ready for high-volume manufacturing. This does not mean that improvements to the current process of record will not happen, but they will take time, and certainly no major material changes are expected in the next few years,” KLA-Tencor’s Preil said. “With that in mind, research continues on several promising avenues. High-k metals to reduce the absorber stack height and mitigate 3D effects have shown some promising early results, but the best films tested to date cannot be etched with the required selectivity and sidewall angle. Some potential films, including nickel—a ferromagnetic material—could cause problems for e-beam writing and inspection tools, although solutions exist for doping the metal to mitigate this effect.”

Another approach is to develop a multi-layer stack with different materials. In 2016, for example, GlobalFoundries, Imec, Lawrence Berkeley National Laboratory and SUNY Poly presented a paper on a multi-layer stack using alternating layers of ruthenium and silicon, as opposed to today’s molybdenum and silicon.

Fig. 6: A new multi-layer material structure. Source: BACUS Newsletter, GlobalFoundries, SUNY Poly, Lawrence Berkeley National Laboratory, Imec

This could reduce mask 3D effects. Others are looking at different multi-layer stacks. “Early research is also underway to develop a multi-layer stack with higher reflectivity than the well-characterized Mo/Si stack universally used in all EUV masks and optics today. While improving the reflector efficiency would be a major improvement in EUV power delivered to the wafer plane, the industry’s collective experience developing near defect-free Mo/Si reflectors clearly demonstrates that any such change would require many years of collaborative effort,” Preil said.

There are other considerations. “As of now, the industry is looking at different materials to accommodate thinner absorber layers to reduce the shadow effect,” Veeco’s Kohli said. “Multi-layer stack material will be a little harder to change but not impossible. We have to take into consideration the cost and availability of the material for large-scale production.”

What’s next?
For 3nm and beyond, the industry is developing a next-generation EUV technology, which is known as high numerical aperture EUV or High-NA EUV.

High-NA will solve some but not all issues. “We will continue to address this issue in High-NA as we do with our prior EUV systems. By reducing magnification in one direction with High-NA, this helps improve the 3D mask effects in that direction. As scaling continues, it will always be important to consider how to best utilize OPC and source-mask optimization to optimize the pattern for the best imaging outcome. This requires a holistic approach to lithography,” ASML’s Lercel said.

At 3nm, though, the industry requires new absorber materials with a thickness of 30nm to 35nm. By then, the industry needs new etching and other tool techniques.

Nonetheless, the industry must get ready for High-NA EUV. In fact, several chipmakers have ordered high-NA EUV tools, meaning the industry is making some serious commitments about the technology.

But the mask industry doesn’t exactly have deep pockets. And it remains unclear where mask makers will find the R&D dollars to help propel High-NA EUV, unless the industry is willing to fund it. “High-NA EUV will also need careful study to optimize the mask film stacks and minimize mask 3D effects. Early High-NA tools may become available in 3-5 years, but the earliest projections for the use of High-NA in volume manufacturing are the middle of the next decade, giving the entire mask making industry ample opportunity to develop the complete infrastructure required to support this technology,” KLA-Tencor’s Preil said.

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