Roaring ’20s For The Chip Industry

2020 was a good year for the semiconductor industry and the EDA industry that fuels it, but 2021 has the opportunity to be even better.

New end application markets continue to open, and what were once seen as technical hurdles are leading to a multitude of innovative solutions, all of which need suitable tooling. No company can afford to invest everywhere, and so for EDA companies, their relative success will be tied to the decisions they make as to where to invest.

Many trends from 2020 continue. “It will be an excellent year going forward,” says Norman Chang, chief technologist at Ansys. “There are more people working on chip design. System companies such as Google, Facebook, and Amazon are working on their own chips that can be used in the data center or other applications. That creates more players in chip design and that directly contributes to the revenue of EDA.”

The drive toward application-specific computing is broadening. “We are in the midst of the hockey stick of application-specific designs, and this is having an impact on design requirements,” says Frank Schirrmeister, senior group director, solution marketing at Cadence. “End-user concerns across the major industry verticals of computing, consumer, mobile, communications, aerospace/defense, automotive, industrial, and health care determine development requirements for designs at the IP, chip and system-levels.”

These designs are seeing a growing number of choices that can be made. “If medical applications were a huge growth area for semiconductors in 2020, IoT has all the makings of reordering the industry dynamics in 2021,” says Lucio Lanza, managing director for Lanza techVentures. “We’re seeing it already as project groups designing new systems in package and chips take advantage of open-source environments and low-cost implementation tools. The result is an explosion of new, cheaper chip designs, and far more rapid solutions delivery targeting a host of new applications. The winners may, in turn, become the high-end chip designs of the future.”

Digitization
While the digitization of the industry has been a trend for a number of years, COVID rapidly accelerated the pace. “The pandemic has accelerated the need to digitalize everything, which will drive demand for further IC and system innovation,” says Joseph Sawicki, executive vice president for Siemens EDA. “Everything will essentially be connected to everything else, and we’ll begin to see AI employed to greater effectiveness in more applications. We will also need to design and test these ever-more complex ICs in the context of their end-systems and even monitor them in the field to attain new levels of safety and improve design quality.”

Work from home has led to many changes. “I expect that many things that were adopted due to COVID will simply remain as an everyday thing,” says Darko Tomusilovic, verification director for Vtool. “Before starting a new project you would have face-to-face meetings, and then regularly during the critical phases of the project. Nobody expects face-to-face meetings anymore. Remote work is here to stay. All conferences became virtual. Our life has become virtual. Anything that can give you a competitive advantage while working from home is of increasing value — faster communication, better ways to connect the team, and things like that.”

Still, many miss the face-to-face interactions. “While it is too early to know if this will be a reality, the semiconductor industry is ready to move away from virtual events and transition back to in-person networking meetings or a combination of virtual and live events,” says Bob Smith, executive director for ESD Alliance, a SEMI Technology Community. “Nonetheless, those of us in the industry keep pushing forward remotely and from home with optimism. Some industry-wide initiatives will gain further focus in 2021, which calls attention to anti-piracy efforts, export regulations, as well as comprehensive online education and training.”

More system choices
Manufacturing and packaging add many new options for how systems can be constructed. “In an increasing number of cases, architects may choose to implement their ICs in a system-in-package (SiP), 2.5D, or stacked die 3D arrangement to reach new power, performance, and area requirements,” says Siemens’ Sawicki. “They may even want to step beyond that and move to the brave new world of photonic ICs, bringing the fiber directly onto the IC or a die on a SiP to achieve even greater system performance.”

These advanced technologies are changing the fabric of the industry. “Foundries will keep offering more and more design services,” says Isabelle Geday, vice president and general manager for the IP Deployment Division of Arteris IP. “They will become super design houses to help integration within the value chain for many system houses and Tier 2 IC companies.”

These technologies are necessary to keep advancing the new kind of Moore’s Law. “We can expect to see further inroads in extending Moore’s Law via the design of system assemblies based on chiplets and/or 3D-IC structures,” says ESD Alliance’s Smith. “New automation and verification technologies will assist in pushing these new approaches from the fringes toward the mainstream. We see growing interest in open-source automation tools and IP with adoption in training and education and potentially for some design activity in mature technologies. Commercial tools and IP will continue to shine as they serve the broader design market and help drive designs below 5nm.”

This is all being driven by the insatiable demand for compute. “Demand for more compute performance in high-performance computing, AI acceleration, gaming processors, and terabit switches has been increasing in the past couple of years,” says Tom Wong, director of marketing, design IP at Cadence. “This is driving the accelerated adoption of 5nm silicon, as well as pushing larger and larger die sizes. I would not be surprised to see 3nm ramping faster than prior nodes in 2021 and 2022. In order to maintain tradeoffs in both performance versus cost and bleeding-edge technology versus time-to-market, we can comfortably predict that die-to-die connectivity and advanced packaging like 2.5D interposer and TSV will gain further acceptance.”

That points to bigger chips. “Design complexity has been pushed to the reticle limit in several industries, fueled by the need to enable complex AI/ML hardware/software, 5G communications, digital transformation, and autonomy,” says Cadence’s Schirrmeister. “For that complexity, 3D-IC assembly techniques enable the individual chiplets to be kept within more favorable yield parameters and ease the creation of new derivative configurations faster without touching the underlying silicon. The resulting development challenges span from verification through digital and custom implementation, embedded software development, assembly, thermal, fluidics, and electro-mechanical aspects that are all interdependent. Assembling new design entities without involving the silicon hardware developer will introduce new verification challenges, especially at the hardware/software interface. Bottom line, integrated platforms will increasingly become a requirement.”

Multi-die solutions will push new communications standards. “We have witnessed the proliferation of die-to-die interfaces and the availability of die-to-die IP in multiple process nodes,” says Cadence’s Wong. “For example, parallel solutions like HBM, the 112G-XSR high-speed serial interface, which is an IEEE standard, and proprietary low-latency die-to-die solutions offering the best bandwidth per beachfront real estate. Die-to-die connectivity is especially popular in server CPUs, gaming processors, and terabit switches/SoCs. Also, look for the excitement surrounding the HBI (high-bandwidth interconnect) interface as the data center folks are really pushing this for die-to-die communications. There is also a lot of activity in ODSA on the OpenHBI Initiative. This may be the final push for chiplets that sport an industry-standard interface to allow for more interoperability than just proprietary solutions.”

This may demand new kinds of verification. “When multiple chips land in a single package, an emulator doesn’t care,” says Johannes Stahl, senior director of product marketing at Synopsys. “Where we start to care — and we saw this emerge in 2020 and it will probably come to fruition in the next few years — is when we need to start paying more attention to the chip interfaces in the same package. You want to make sure that you emulate the communication more closely, almost going into complete analog signal emulation. We published a paper about that as a research topic with DARPA a few years back, and now that’s coming into the commercial space. We expect companies to do this more and more in the next few years.”

The drive toward domain-specific architectures will continue. “The insatiable demand for neural network compute is already providing the motivation for a new class of processor optimized specifically for neural networks,” says Ian Bratt, fellow and senior director of technology for Arm. “New processor architectures with tensor-level operation abstractions will be present in nearly every computing platform, running the majority of computing cycles. This new class of processor will achieve orders of magnitude efficiency gains over traditional computing platforms, heralding an industry-wide shift in the computing landscape.”

Stretching verification
The verification landscape also is changing. “As designs become more complex and connected, there’s a greater need to not only verify your IC designs functions according to your specification, but also to verify and validate that they work in the context of the end-system,” says Sawicki. “This is especially true if the system needs to comply with a particular set of protocols or standards, or if safety and security are mandatory. Increasingly, to do this correctly requires verification and validation technology that moves beyond the traditional realm of what’s been considered EDA. Advanced systems companies — especially those involved in the automotive/transportation industry — are developing digital twins where they can thoroughly test, debug and refine their systems. These are running in the virtual world across the electrical and mechanical domains with real-world input before committing to manufacturing. Digital twins will become even more useful as autonomous driving becomes connected to the grid of smart infrastructure.”

This may require rethinking of some issues. “The biggest challenge is the end-to-end system,” says Colin McKellar, vice president of verification platforms for Imagination Technologies. “We need to be able to point at the full ecosystem and say we’ve validated or verified that all of these security and functional safety elements have been met. It is very difficult to prove that you’re done — or prove that when you get to the next level up, into the application or into the factories — that everything you did holds true. The world of functional safety is maturing, but most of it is about a process that you can show to an auditor that you’re really thought about this, and you’ve minimized the risks.”

AI/ML architectures have a hierarchy of verification needs. “For this type of design, one of the biggest concerns in the amount of arithmetic logic,” says Kiran Vittal, product marketing director for verification at Synopsys. “They have multipliers and adders mainly for the CNN networks. Validating those in simulation is very difficult and would take years to do the necessary simulations. You need some kind of equivalence checking that takes a C model and performs equivalence checking against the RTL representation.”

Then you need different tools that can take a regular structure of those verified cells to verify the system-level capabilities. And finally, you need a third set of tools for when software is mapped onto hardware.

Security is forcing change, too. “Security will take on a new meaning in 2021,” says Jay Alexander, senior vice president and chief technology officer for Keysight. “Developers will address potential security issues, including security testing, much earlier in the design cycle. Greater emphasis will be placed on how products will be deployed, the use of touchless and contactless technology, removing human intervention, and fully automating networks that self-heal.”

Security is requiring new forms of verification. “There is an emergent need for side channel analysis, not only for the SoC, but also important for 3D-IC,” says Ansys’ Chang. “We are seeing that more side channel information can be leaked from power consumption, from power noise, from dynamic voltage analysis, from thermal analysis or electromagnetic noise emanating from the chip. Usually, it takes thousands of cycles, or millions of plain text packets to crack a key. So that puts a lot of demand on the analysis capabilities of tools. When we do sign off for dynamic voltage drop, we only need about 20 cycles, focusing on peak power cycles. However, for a side-channel information analysis or side-channel leakage analysis, it requires thousands of cycles.”

Open source
The RISC-V open-source ISA took the industry by storm last year. Verification is playing catch up. “The community needs to invest in standards for the verification of these open-source, customizable CPU cores,” says Olivera Stojanovic, senior verification manager for Vtool. “Every company does it a slightly different way today. With every new project, we have to invest too much time to get a basic test case running, compiling, and establishing some sorts of communication between the testbench and the processor, and the software running on it. So even though we all have a similar methodology, in the end everybody does it differently.”

That is causing a bifurcation in the market. “The market is divided into two areas,” says Synopsys’ Stahl. “One is a market of big guys that can afford to have processor experts and want some kind of infrastructure around it to bootstrap themselves. Then there is the market of companies that do not have expertise, and what they’re simply doing is using one of the available RISC-V IP cores. It is then expected that the cores are pre-verified by the IP provider.”

This is creating new kinds of IP companies. “Open source with added services is the up-and-coming business model for CPU hardware IP,” says Arteris’ Geday. “IP reuse will grow as highly sophisticated and ultra-specialized functions, some requiring certification, that cannot be designed by all SoC designers. We see many examples of this in the AI field today.”

Lifecycle management
The product is no longer complete when the chips come back from the fab. “Enterprises will speed transformations using software that improves productivity, efficiency, accuracy, security, and time-to-market,” says Keysight’s Alexander. “They will do this by collecting and acquiring information digitally, coupled with the use of advanced analytics and data visualization to gain insights needed to accelerate innovation.”

This is similar to the incorporation of logic for Design for Test. “An increasing number of systems companies will begin to leverage silicon lifecycle management technologies,” says Siemen’s Sawicki. “This enables companies to insert IP blocks into their design during the early phases of the IC design process. These IP blocks monitor such things as performance, power consumption, errors, and even security breaches inside the IC. This information can be used to identify problems and predict wear, trigger a warning for the operator, schedule preventative maintenance, or even be used to further refine design and manufacturing for derivative/future-generation ICs.”

Silicon monitoring becomes an extension of the digital twin. “Silicon monitoring systems provide thermal hotspot monitoring, voltage monitoring, and also latency monitoring,” says Chang. “This presents another opportunity for providing digital twins, to work together with in-field monitoring sensors on-chip or in-system. We can provide a simulation solution, such that when we see a problem coming from the in-field monitoring sensors we can provide a diagnostic solution very quickly, combined with the in-field sensor monitoring solution.”

More focus on software
Increasing amounts of functionality are coming from software. “Demand for software is outstripping traditional methods for developing it,” says Mark Hambleton, vice president of software for Arm. “As time goes on, we will shift from developing applications to developing tools that can develop applications on our behalf.”

That level of functionality will require some changes. “Up until the last year, unlocking the power of hardware adaptability was unattainable for the average software developer and AI scientist,” says Nick Ni, director of product marketing for AI and software at Xilinx. “Specific hardware expertise was required but new open-source tools are empowering software developers with adaptable hardware, while accelerating productivity for hardware designers. In 2021, with this new ease of programming, FPGAs, and adaptable SoCs will continue to become more accessible for hundreds of thousands of software developers and AI scientists making them the hardware solution of choice for next-generation applications.”

Our virtual work environments are also pushing more functionality into software. “A hybrid workforce, social distancing, and other dilutions of historical work efforts will accelerate software enablement for product design and development,” says Alexander. “Software-led processes will play an enormous role in 2021. Product design, R&D, testing, manufacturing/production, and diagnostic troubleshooting will be accomplished remotely through software-led solutions. Companies will rely on software to support a remote workforce by leveraging the cloud and providing advanced computation abilities. Marketing engagements, customer interactions, and customer support will each be at the center of digital transformations in 2021. Greater personalization in marketing and communication is assured.”

Startups, China, and people
The events of the last couple of years are transforming the industry in several ways. “One area we need to watch is the number of startups in Silicon Valley or any other place,” says Chang. “This is due to COVID-19. It is more difficult to see the founders, and if you want to give them a chunk of money, you want to see their faces. You want to feel their personality. This has become more difficult, and I think we will see a reduction in 2020 compared to 2019. Then we need to see if there will be a further reduction in 2021.”

Politics is important. “Political leaders come and go,” says Graham Kill, executive chairman for Cylynt. “During their tenure, trade wars wax and wane. What is a constant is national competitiveness on a global scale. 2020 saw the continuation of overt and the covert state-sponsored IP acquisition by the players, including by those with aspirations to ‘level up’ and later dominate key technology areas, such as silicon manufacturing. In 2021, we could see more of the fruits of their IP ‘procurement’ labors begin to manifest. The tip of the iceberg might be revealed, yet the ice below the waterline might only be fully comprehendible in subsequent years.”

Internationally, China is the one to watch. “China will be the country driving growth,” says Geday. “They have startups mushrooming in every industry segment, and government initiatives are helping to fund EDA platforms. China is looking for independence from Western countries and is thus redesigning a lot of existing SoCs.”

This also is affecting the labor pool. “We used to get new designers coming from China, Taiwan, and India,” says Chang. “They supplied a lot of fresh graduates, and they had a very good education from U.S. colleges. But with the existing policies, some of the people companies could hire were prohibited. That means companies have to be flexible, and they have to work with engineers in China or India. That requires exceptionally good remote office methodologies to enable engineers to work outside of the U.S. Some companies have managed this better than others, but hopefully we will see the reverse of this policy, and more engineers will come from China or India or Taiwan, that can be employed locally in the U.S.”

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