Increasing interconnect density is making it harder to guarantee these devices will work as expected.
Ensuring the quality of silicon and organic interposers is becoming harder as the number of signals passing through them continues to grow, fueled by more chiplets, higher processing demands, and more layers of devices assembled in a package.
Interposers initially were viewed as relatively simple conduits. That perception has changed rather dramatically in recent years with the growing focus on heterogeneous integration. There are more layers being added above and below the interposer, more possibilities for signal interference, and more thermal effects from increased processing demands that can cause warpage. The result is a higher likelihood of reduced yield, and increased time and resources spent on testing and inspecting these devices.
And that’s just for starters. The distance that signals need to travel between die and the final package substrate depends on how many layers of metal or organic materials they need to pass through. The longer the distance, the more power needed to drive those signals, and the more heat that needs to be dissipated. That is compounded by the need to process more data more quickly, particularly with AI, which puts added strain on interposers and makes them harder to manufacture, magnifies latent defects, and increases the intensity of lattice mismatch effects between materials.
Collectively, that makes screening for process defects in interposer interconnects and micro-bumps much more difficult. Engineers must carefully consider the limitations of electrical and optical methods. At the same time, they need to continuously update the methods used to keep pace with decreasing feature sizes.
Fig. 1: 2.5D package with silicon interposer. Source: Siemens EDA
Fig. 2: 2.5D advanced package with organic interposer. Source: Bruker
Guaranteeing known good interposers requires a combination of electrical test, inspection, and metrology. Due to probing challenges, interposer test relies upon probe pads dedicated for test. But available die area also limits the number of test pads, and when coupled with an interposer packed with passive interconnects, it places limits on electrical test coverage.
Organic and inorganic interposers require inspection during the interconnect formation in the redistribution layers (RDL). In addition, inspection and metrology are both needed to ensure interposer micro-bump co-planarity.
“Testing known good dies (KGD) and known good interposers (KGI) in 2.5D/3D packages presents a number of challenges that must be considered,” Jeorge Hurtarte, senior director of product strategy for SoC marketing at Teradyne, and co-chair of the IEEE Heterogeneous Integration Roadmap Test Technology Working Group, observed in a recent article. “Integration is complex, with dies and interposers in a 3D stack resulting in multiple layers of interconnections and varied functionalities. The miniaturization of these components adds difficulty due to intricate connections like through-silicon vias (TSV) and reduced physical space for testing probes.”
This reduced area lends itself to lower test coverage. “Known good die (KGD) test is recommended for dies/chiplets in pre-bond testing to ensure the assembly of 3D ICs (including 2.5D and 3D) has high yield,” said Vidya Neerkundar, product manager for DFT flows, Tessent silicon test solutions at Siemens EDA. “However, for interposers, there is a pretty good die (PGD) test that refers to a less rigorous testing procedure, where KGD is not possible until 3D stack assembly. This is simply a connectivity-type test, and in the future it may need other methods as interposers become more complex. Even PGD can still identify issues early, and may be the cost-effective viable option.”
Limited electrical test coverage creates a greater reliance on 100% inspection, and at times 100% metrology coverage during the interposer manufacturing process, from RDL through micro-bumps. Inspection identifies common defects, while an extensive list of metrology measurements — including line width and spacing, layer thicknesses, bump height and diameter — can affect interposer yield.
“There is a need for 100%, because you’re committing very expensive dies on it,” said Monita Pau, strategic marketing director for advanced packaging at Onto Innovation. “You want to make sure there’s nothing wrong before you put in those very expensive memory dies or logic dies on top of it. There are inspection and metrology steps used for organic and inorganic interposers. Differences in measurement approaches depend on the material used, as well as the resolution of the patterns. At the moment, inorganic interposers have a finer feature size than organic interposers.”
As feature sizes and pitches decrease, the measurement challenges increase, particularly for micro-bumps.
Fig. 3: Decreasing micro-bump, C4 bump, and TSV sizes. Source: ASE
“Reductions in bump pitch pose significant challenges in failure localization and analysis,” noted Sammy Perets, product marketing manager at Bruker. “Direct probing of bumps is challenging owing to restricted access / limited real estate for test pads. Pitch reduction has driven reductions in spatial resolution for optical inspection systems.”
Electrical test
Despite being manufactured in mature technologies, electrical test of interposers is necessary to minimize yield loss related to stacking dies on a defective interposer.
“Usually, the silicon interposer is made with a very mature silicon node,” said Shinji Hioki, ACS pre-sales director at Advantest America. “The silicon interposer vendor does not necessarily perform electric testing on all interposer nets, but I expect some level of process monitoring to be implemented to ensure there are no process excursions.”
Authors of the Heterogeneous Integration Roadmap Test Technology Chapter [1] summarized the interposer test requirements as follows: “Known good interposers (KGI) are vital to ensure adequate yielding advanced packages. Silicon interposers include interconnect and through-silicon via (TSV) structures. Mechanical integrity of these structures during the manufacturing process ensures electrical performance. D/C and A/C transient pre-bond testing of interposers helps in screening micro-void and pinhole defects. Testing of interposers may require custom test fixture development and test insertion, which impacts the overall product cost.”
While checking basic connectivity is a straightforward exercise, the reliance upon a limited number of test pads presents a challenge to achieve test coverage for all nets. The continued reduction of micro-bump sizes only magnifies that challenge.
“For instance, the direct probing of micro-bumps at these pitches requires the use of test pads to mitigate the lack of direct probing method,” said Advantest’s Hioki. “Placement of testing pads (to avoid actual touch down to micro-bump) and probe needles to touch down those pads can be skinnier, too.”
Even probing test pads becomes a concern. “Production test hardware design requires careful considerations,” said Vineet Pancholi, senior director of test technology at Amkor. “At the wafer level, with the pad sizes and pad pitches becoming smaller (<60 to 75 µm) and the density of pads increasing (25,000 to 50,000), it is important to realize that the probe card technologies are not scaling at the same rate, and the costs are skyrocketing disproportionately.
Fundamentally, interposer test coverage requires testing of the metal interconnects and TSVs. But as direct probing of micro-bumps is not possible, not every TSV and metal interconnect will be tested via a test pad. With limited access via test pads, active dies must rely on DFT-based test approaches for high test coverage. This approach is not possible with passive interposers.
Thus, the area limitations of test pads and the high number of TSVs and inter/intra-die nets directly contributes to the impossibility of testing all of them.
In a 2013 ITC paper [2], TSMC engineers described their test approach to assure “pretty good die” that worked within these constraints. First, they noted that power/ground signals are either a single micro-bump-to-C4 using a TSV (T2), or multiple micro-bumps-to-C4 using a TSV (T3). The remaining micro-bumps consist of the inter-die and intra-die interconnects (T1). To accomplish a test solution, selected nets and TSVs are connected to a test pad. They noted that T2 and T3 connections with the same signal can share a test pad. However, T1 connections only permit a single micro-bump to a single test pad.
“For interconnect testing, we use dummy metal (extra metal) to connect micro-bump pairs of a net under-test to near-by probe pads available at the center of common micro-bump/TSV structures,” wrote the authors. “As the added dummy metal increases the loading of the signal and can degrade its performance, it is very important to minimize the length of the added dummy metal. Finding the optimal micro-bump and probe-pad pair that minimize total added wire length is a separate problem.” [2]
Fig. 4: TSMC connections to test pads. Source: A. Meixner, Semiconductor Engineering
Selecting the interconnect nets for this test strategy requires balancing the availability of test pads, the potential performance degradation due to the dummy nets, and an interconnect’s impact on final yield. In a 2013 ECTC paper [3], TSMC engineers described the algorithms used to select the nets. “It is quite important to have a good methodology to help designers decide the utilization of probe-pad pairs while keeping the introduced latency small. As a result, we formulate this problem as follows: Probe-pad pairs and nets assignment: Given a set of probe-pads placed at different islands, a set of target testing nets and each net has the attached micro-bumps, determine an assignment for the connection between probe-pads and micro-bumps such that the total introduced latency is minimized.”
To determine the probe-pad and micro-bump assignment, the engineers deployed two algorithms. The first algorithm, priority-based probe-pad pairs and nets assignment (PPNA), considers nets in order of criticality and based upon net-length. However, this approach had two drawbacks. First the distance measurement for determining order proved to be insufficient. Second, the assignment could not consider the whole problem — in particular, the limited number of test pads — which likely leads to a suboptimal solution. Therefore, they used a second algorithm that used a simultaneous assignment algorithm with a minimum-cost maximum-flow formulation. The proposed maximum-flow based algorithm (MFPNA) addressed the interplay between test pad usage and net criticality.
Inspection and metrology of RDL and micro-bumps
Metrology and inspection provide interposer screening, which is essential due to incomplete test coverage of all the nets within the interposer and no coverage of micro-bump quality. To do so with confidence requires complete coverage using metrology and inspection throughout the interposer manufacturing process. Both organic and inorganic interposers also require quality checks of the RDL interconnect and layers, the micro-bumps, and for inorganic interposers, their TSVs.
Interposer RDL inspection looks for bridges, opens, and other defects. Metrology monitors line width, spacing, and depth at photoresist development and after copper deposition.
“Besides inspection, there are a lot of different metrology steps performed as they are building the interposer, which include the line width and space,” noted Onto’s Pau. “But they also monitor thickness and height. Thickness is important for photoresist or dielectric coating. Engineers want to make sure that the coating is uniform, and that requires different metrology methods.”
Differences between organic and inorganic interposers impact the methods used. “The resolution of the line and space are quite different between inorganic interposer and organic interposer,” Pau said. “Because the feature size is smaller with inorganic interposers, the inspection requirement is more stringent than for organic interposers. Also, they use different materials. The source of noise differs, depending on whether you’re looking through the polyamide versus an inorganic oxide layer. This leads to differences in noise control.”
Others concur that material properties impact measurement, and they noted that form factor differences add yet another set of challenges.
“With silicon interposers it’s easier to perform metrology, mobilizing standard 300mm wafers with high degree of flatness and low warpage,” said Soham Dey, senior product line manager at Bruker. “The silicon surface provides a clear reference plan from which the depth of the TSV can be derived with tens of nanometers precision. Organic interposers, such as ABF or BT, are often based on a 600 x 600mm² panel with warpage up to couple millimeters. Panel handling and flattening causes challenges, both with respect to the crash of optical objectives and throughput. The former is addressed by the white light interferometry (WLI) principle, mobilizing long working distance objectives (4 to 5mm) while preserving nanometer-level vertical precision. The latter is addressed by us with an external focusing device allowing fast auto-focus. Finally, an organic interposer surface is more challenging to measure with optical techniques due to poor reflectivity and contrast, which WLI alleviates through a high signal-to-noise ratio fringe.”
Measuring the micro-bump height ultimately enables an assessment of coplanarity across a set of interposers, regardless of whether they’re on a panel or on a wafer. Measurements of final bump height is required. Surprisingly for failure detection and process control engineers measure thin films in the middle of micro-bump processing.
Fig. 5. Micro-bump characteristics during processing. Source: Nordson Test & Inspection
“Initially I didn’t realize how important measuring some of those thin films were to customers,” said John Hoffman, computer vision engineering manager at Nordson Test & Inspection. “They want to measure those films before they continue the manufacturing process because this determines how large your copper pillars become. They want to catch failures that early. And they want to measure thin film heights it in situ, i.e., in the middle of the process. You’re trying to measure film with these characteristics. But due to the surrounding structures, it’s not like a typical thin film measurement.”
These types of measurements are impacted by material reflective properties and aspect ratios.
Fig. 6: Measuring thin films in middle of copper pillar processing. Source: Nordson Test & Inspection
As feature sizes shrink, every metrology and inspection technique faces issues to which they must adapt. Specifically, the shrink of lateral and vertical dimensions triggers two challenges. The first relates to the need for submicron lateral resolution and nanometer vertical resolution. Then there’s the issue of the increasing aspect ratio, which prevents light reflecting from the bottom of a structure for TSV and RDL.
“The white light interferometry (WLI) profiler helps resolve those challenges through independent vertical position calculations on each pixel of the camera and nanometer vertical resolution from interferometric algorithms,” said Bruker’s Dey. “It also enables the measurement of aspect ratios till 20:1 through collimated beam from long working distance objective. For instance, the latest TSVs with a 2µm opening and up to 40µm are successfully measured in case of WLI. Depths for all TSVs included in the field of view are recorded within a single vertical scan, allowing high speed screening without the hurdle of modeling.”
Other metrology and inspection providers noted these challenges as they relate to micro-bump formations.
“As you go from larger bumps and pitch to smaller bumps and smaller pitches there comes a twofold difference,” said Onto’s Pau. “One, the bumps are getting smaller. To meet the resolution you need to consider, is your tool sensitive enough to see the small bumps? Is the signal strong enough for you to have a high enough signal-to-noise ratio to see the bump? The other part is that there are a lot more bumps than before, so you have a lot more data to collect and process.”
And with optical inspection, the camera has a fixed pixel array. “The single biggest challenge facing us is just keeping up with the node size reduction,” said Nordson’s Hoffman. “If you have a micron feature, we need so many pixels across that to do a good inspection for 3D or 2D. I’m doing optical inspection and my camera has a 5,000 x 5,000 pixel array. If the node sizes are cut in half, that means my inspection size is shrunk by a factor of four, and this naturally increases my inspection time by a factor of four.”
It’s not just the pixel size that affects optical measurements,” he said. “With phase profilometry we use a projector that shines down, and then we observe the structured light patterns with a camera. And there are physics limitations where if you get pixel size down too small, measurements start overlapping. You have to think about alternative ways of making that measurement. Going from 12 microns per feature to 7 microns you’re basically doubling the number of pixels. Now I’m just not achieving the speed you want. But the way that we get a lot of our performance is through bespoke optics. We make special optics to make these measurements possible. And with this rate of change you’re respinning optics every year.”
Conclusion
As the lowest cost component of an advanced package product, defective interposers have a costly impact. Effectively screening both organic and inorganic interposers significantly depends upon metrology and inspection, because electrical test has limited coverage, and it’s the only means to screen micro-bump quality. Finally, metrology steps provide engineers with essential data for process control.
References:
Related Reading
Advanced Packaging Drives Test And Metrology Innovations
Complex devices are pushing test and metrology tools to their limits, but solutions are coming online.
Progress In Wafer And Package Level Defect Inspection
Advances in imaging systems aim to improve throughput without sacrificing measurement accuracy.
Many More Hurdles In Heterogeneous Integration
More resources will be needed for IC-to-package design, process extendibility, and improved reliability.
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