Week In Review: Manufacturing, Test


Chipmakers TSMC has introduced another version of its 4nm process technology. The process, called N4X, is tailored for high-performance computing products. Recently, TSMC introduced another 4nm process, called N4P, which is an enhanced version of its 5nm technology. N4X is also an enhanced version of its 5nm technology. N4X, however, offers a performance boost of up to 15% over TSMC’s N5 pro... » read more

The Return Of DAC In-Person


Apart from masked faces everywhere, you could be excused for not knowing that there was a pandemic going on. Sure, the numbers were down, the show floor was smaller, and most of the parties didn't happen, but everyone was so happy to be able to bump elbows with their colleagues. Buttons were available for attendees to show the level of comfort they had with various types of greetings, from "... » read more

Week In Review: Manufacturing, Test


Chipmakers China’s Tsinghua Unigroup is in trouble. The group is the parent company of China’s YMTC, a 3D NAND supplier, and other chip ventures. It is close to moving into bankruptcy proceedings. Now, a consortium led by Alibaba has emerged as the frontrunner to take over Tsinghua Unigroup, according to a report from Bloomberg. That deal would keep the company afloat, the report said. ... » read more

A Broad Look Inside Advanced Packaging


Choon Lee, chief technology officer of JCET, sat down with Semiconductor Engineering to talk about the semiconductor market, Moore’s Law, chiplets, fan-out packaging, and manufacturing issues. What follows are excerpts of that discussion. SE: Where are we in the semiconductor cycle right now? Lee: If you look at 2020, it was around 10% growth in the overall semiconductor industry. ... » read more

Week In Review: Manufacturing, Test


Chipmakers AMD has rolled out its new MI200 series products, the first exascale-class GPU accelerators. Using a fan-out bridge packaging technology, the MI200 series are designed for high-performance computing (HPC) and artificial intelligence (AI) applications. The MI200 series accelerators feature a multi-die GPU architecture with 128GB of HBM2e memory. Typically, the HBM2e memory stack a... » read more

Week In Review: Manufacturing, Test


Chipmakers After years in the works, GlobalFoundries is finally a public company. But on its first day of trading on Thursday (Oct. 28), shares of the foundry vendor slipped a bit. GF finished its first day of trading at $46.40. This compares to the $47 per share it priced in the initial public offering (IPO), according a report to Reuters. The chipmaker has a market capitalization of about $2... » read more

Scaling Bump Pitches In Advanced Packaging


Interconnects for advanced packaging are at a crossroads as an assortment of new package types are pushing further into the mainstream, with some vendors opting to extend the traditional bump approaches while others roll out new ones to replace them. The goal in all cases is to ensure signal integrity between components in IC packages as the volume of data being processed increases. But as d... » read more

What’s Next For Transistors And Chiplets


Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Building Complex Chips That Last Longer


Semiconductor Engineering sat down to talk about design challenges in advanced packages and nodes with John Lee, vice president and general manager for semiconductors at Ansys; Shankar Krishnamoorthy, general manager of Synopsys' Design Group; Simon Burke, distinguished engineer at Xilinx; and Andrew Kahng, professor of CSE and ECE at UC San Diego. This discussion was held at the Ansys IDEAS co... » read more

Data Tsunami Pushes Boundaries Of IC Interconnects


Rapid increases in machine-generated data are fueling demand for higher-performance multi-core computing, forcing design teams to rethink the movement of data on-chip, off-chip, and between chips in a package. In the past, this was largely handled by the on-chip interconnects, which often were a secondary consideration in the design. But with the rising volumes of data in markets ranging fro... » read more

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