Speeding Up The Design Process


A rush to plant a stake in new markets, coupled with uncertainty about how to generate a reasonable return on investment in those markets, is ratcheting up pressure on chipmakers. They now must come up with more customized solutions in less time, frequently in smaller volumes, and with the ability to modify them in shorter time spans if market opportunities shift in unexpected ways. This aff... » read more

Why Instrumentation Isn’t Optional


When writing code it is often useful to add informational statements that give an insight into control flow and data management as well as aiding in observation of the actual code at runtime. As such, instrumentation is an important component of code running on a live system. The proliferation of "printf" debug statements, whereby data is output to a console, is testament to this. Sending te... » read more

Blog Review: July 27


Mentor's Tom Fitzpatrick investigates how to add new behavior to an existing testbench with the UVM factory class. Synopsys' Srinivas Vijayaragavan and Pooja Gupta dig into new features of SAS 24G, including how its effective speed was doubled to 24G though signaling rate remains at 22.5G. Cadence's Paul McLellan highlights a presentation from the SEMI/Gartner Market Symposium focused on ... » read more

How Cache Coherency Impacts Power, Performance


As discussed in part one, one of the reasons cache coherency is becoming more important is the shared common memory resource in designs today. Various agents in the design want to access the data the fastest they can, putting pressure on the CPU complex to manage all of the requests. Until a generation ago, it was okay for the CPU to control that memory and have access to it, as well as be t... » read more

The Week in Review: IoT


Deals The big news of the week, of course, is SoftBank Group’s proposed acquisition of ARM Holdings for a breathtaking $32.2 billion in cash. In announcing the deal, the companies made it abundantly clear that the proposed acquisition is chiefly about Internet of Things technology. “When I think about the investment and the commitment that’s going to be required to develop the future te... » read more

The Week In Review: Design


Tools Synopsys updated its static timing analysis tool to use smart engineering change order (ECO) technology, which the company says reduces memory requirements by 5X and speeds runtime by 2X. The release also allows more scenarios on a single server, or flexible distribution to take advantage of customers' private compute clouds. IP Synopsys released MIPI display and camera interface... » read more

5 Takeaways From Semicon


As usual, the recent Semicon West trade show was a busy, if not an overwhelming, event. The event, which took place in San Francisco in early July, featured presentations on the usual subjects in the semiconductor and IC-equipment sectors. There were sessions on 200mm, next-generation processes, transistors, lithography, MEMS and many others. In no particular order, here are my five ta... » read more

To 7nm And Beyond


Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], and Thomas Caulfield, senior vice president and general manager of Fab 8, sat down with Semiconductor Engineering to discuss future directions in technology, including the next rev of FD-SOI, the future of Moore’s Law, and how some very public challenges will likely unfold. SE: What do you see as the... » read more

Blog Review: July 20


Applied's Er-Xuan Ping addresses the challenges facing materials and processing in a changing memory landscape, and the opportunities that may arise. Cadence's Paul McLellan looks at teaching neural networks to perceive things more like humans do, through German traffic signs. Mentor's Colin Walls digs into managing timing and peripherals in embedded systems. Synopsys' Robert Vamosi ch... » read more

Can Verification Meet In The Middle?


Semiconductor Engineering sat down to discuss these issues with; Stan Sokorac, senior principal design engineer for [getentity id="22186" comment="ARM"]; Frank Schirrmeister, senior group director for product marketing for the system development suite of [getentity id="22032" e_name="Cadence"]; Harry Foster, chief verification scientist at [getentity id="22017" e_name="Mentor Graphics"], Bernie... » read more

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