tag: ARM

DAC Is Dead? Long Live DAC!
By Kurt Shuler - 27 Jun, 2013 - Comments: 0

By Kurt Shuler I have long decried the declining attendance at the ACM/EDAC/IEEE Design Automation Conference (DAC), especially in regard to this trend’s adverse effect on continuing professional education (CPE) opportunities for our industry’s engineers. (See my May 2011 article, “The Trouble With Tradeshows, for more.) In fact, for those of you who know me personally, I have sometimes ... » read more

Experts At The Table: Performance Analysis
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down with Ravi Kalyanaraman, senior verification manager for the digital entertainment business unit at Marvell; William Orme, strategic marketing manager for ARM’s System IP and Processor Division; Steve Brown, product marketing and business development director for the systems and software group at Cadence; Johannes Stahl director o... » read more

The Week In Review: June 21
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

VLSI Kyoto – The SOI Papers
By Various Writers - 19 Jun, 2013 - Comments: 0

By Adele Hars There were some breakthrough FD-SOI and other excellent SOI-based papers that came out of the 2013 Symposia on VLSI Technology and Circuits in Kyoto (June 10-14, 2013). By way of explanation, VSLI comprises two symposia: one on Technology; one on Circuits. However, papers that are relevant to both were presented in “Jumbo Joint Focus” sessions.  The papers should all b... » read more

Rethinking Big Iron
By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler One size does not fit all when it comes to the server market, and that may be the best option for low-power processor makers to gain a toehold in a world that until now has been almost laser-focused on performance. Even higher-performance versions of low-power processing architectures are starting to show up inside of datacenters. Many are application-specific ... » read more

Drowning In Data
By Ed Sperling - 13 Jun, 2013 - Comments: 0

By Ed Sperling The old adage, “Be careful what you wish for,” has hit the SoC design market like a 100-year storm. After years of demanding more data to understand what’s going on in a design, engineering teams now have so much data that they’re drowning in it. This is most obvious at advanced process nodes, of course. But it’s also true these days at more mainstream nodes such as... » read more

The Week In Review: June 7
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling For all the hesitation about moving the Design Automation Conference to Austin, it turns out that Austin has a lot of hardware engineers. In fact they flooded into the conference, turning it into one of the most successful in recent years and setting new records in multiple areas. Even Texas Gov. Rick Perry showed up to see what all the fuss was about. Mentor Graphics added c... » read more

Experts At The Table: The Growing Signoff Headache
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design ... » read more

Scaling The Lowly SRAM
By Mark LaPedus - 05 Jun, 2013 - Comments: 0

By Mark LaPedus Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one major challenge that is often overlooked in the equation—scaling the lowly static RAM (SRAM). In one key application, SRAM is the component used to make on-chip cache memories... » read more

Experts At The Table: The Growing Signoff Headache
By Ed Sperling - 31 May, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design... » read more

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