tag: ARM

SoCs Go Mainstream
By Ed Sperling - 22 Mar, 2012 - Comments: 0

By Ed Sperling The monolithic ASIC, which has been the bread-and-butter of chipmakers for decades, is giving way to systems on a chip among mainstream chipmakers and at mainstream process nodes. This shift has been overhyped, overpromised and slow to materialize. While SoCs have been common for years in mobile electronics and for high-performance platforms such as gaming consoles, they have... » read more

New Winners And Losers
By Ed Sperling - 22 Mar, 2012 - Comments: 0

The realignment of the semiconductor industry has begun, most of it beneath the radar screen. In a disaggregated supply chain, any piece in isolation looks insignificant. But taken together, these shifts begin to paint a picture of a broad realignment and refocusing of the entire industry that ultimately will cement the fortunes of some and create new winners and losers out of others. The fi... » read more

FD-SOI – Consortium Results (Part 2 of 3): Power and Performance
By Various Writers - 21 Mar, 2012 - Comments: 0

The results of the most recent SOI Consortium benchmarking study detail the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. This 3-part blog series looks further at some of the implications. ~~ Fully depleted transistor architectures such as Planar FD-SOI, FinFETs (which is also a fully-depleted technolog... » read more

Experts At The Table: IP
By Ed Sperling - 16 Mar, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to talk about IP with John Goodenough, vice president of design technology and automation at ARM; Simon Butler, CEO of Methodics; Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys, and Neil Hand, product marketing group director at Cadence. What follows are excerpts of that discussion. LPE: Are w... » read more

FD-SOI Workshop ppts – STM’s 1st 28nm FD-SOI product line
By Various Writers - 12 Mar, 2012 - Comments: 0

The SOI Consortium’s 6th FD-SOI workshop, held just after ISSCC, yielded some exciting news. Most of the presentations are freely available for downloading from the SOI Consortium website. Here are the highlights. STMicroelectronics In a terrific presentation by Giorgio Cesana, Marketing Director at STMicroelectronics, he revealed that the company would be releasing a major product line b... » read more

Experts At The Table: IP
By Ed Sperling - 08 Mar, 2012 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to talk about IP with John Goodenough, vice president of design technology and automation at ARM; Simon Butler, CEO of Methodics; Navraj Nandra, senior director of marketing for DesignWare analog and mixed signal IP at Synopsys, and Neil Hand, product marketing group director at Cadence. What follows are excerpts of that discussion. LPE: Where ... » read more

FD-SOI – Recent Consortium Results (Part 1 of 3): Manufacturing
By Various Writers - 05 Mar, 2012 - Comments: 0

The most recent SOI Consortium benchmarking study regarding 28nm and 20nm FD-SOI results (silicon-calibrated simulations at the 28nm node of complex circuits including ARM cores and DDR3 memory controllers) covered a lot of ground. This post is part 1 of a 3-part blog series that will be highlighting key points with respect to: 1. manufacturing; 2. power & performance; 3. 20nm benchmarking ... » read more

Step Away From the Spreadsheet
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ann Steffora Mutschler Engineers today spend more than a quarter of their time trying to meet power specifications. A survey of more than 700 engineers by Calypto illustrates just how important and time-consuming power management is today for engineering teams. As consumer devices grow ever more complex, the need to deal with, analyze and optimize power at not just the RTL but at the sys... » read more

Processor Subject To Change
By Ed Sperling - 09 Feb, 2012 - Comments: 0

By Ann Steffora Mutschler With power complexity driving sophisticated management techniques, SoC design engineering teams are turning to a new class of customizable processor architectures from ARM, CEVA, NVIDIA, Qualcomm and Tensilica and others to take advantage of the best in power saving techniques. While these new architectures are novel approaches, the concepts are not especially new,... » read more

The Next Big Challenge
By Ed Sperling - 12 Jan, 2012 - Comments: 0

By Ed Sperling Software is the next big target in the quest to make electronics more energy efficient, but it’s proving a far bigger challenge than most systems architects originally believed it would be. There are several very large big problems to deal with in software. Writing efficient code for small processors isn’t one of them. In fact, the proliferation of small processors across... » read more

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