tag: Mentor Graphics

Blog Review: April 23
By Ed Sperling - 23 Apr, 2014 - Comments: 0

Mentor’s John Day looks backward through a smart rearview mirror from Nissan. No glare, even at night or at sunset, and a wider field of vision. You have to wonder why this technology took so long. Synopsys’ Karen Bartleson wonders when the IoT will actually arrive, given the delay in durable goods, a concern over security and the effects of government regulation. Answer: When we stop ta... » read more

Cadence Gobbles Up Jasper
By Brian Bailey - 21 Apr, 2014 - Comments: 4

2012 was the year that everyone remembers Synopsys going on an acquisition binge, but 2014 will go down as the year that Cadence Design Systems decided that EDA was worth investing in. Rather than placing investment bets outside of its core competence, Cadence bought Forte in February and now adds Jasper Design Automation to its fold. Jasper started life as Tempus Fugit in 1999 and became Ja... » read more

The Week In Review: Design
By Ed Sperling - 18 Apr, 2014 - Comments: 0

Certifications TSMC certified Mentor Graphics’ DFM, place and route and custom IC tools, as well as its SPICE simulator, for the 16nm finFET process.  The foundry also certified Cadence’s digital and custom/analog tools for that process, including physical verification, QRC extraction, timing sign off and its power integrity solution. And it certified Synopsys’ digital and custom soluti... » read more

Improving Yield Of 2.5D Designs
By Ann Mutschler - 18 Apr, 2014 - Comments: 0

While progress is being made on the packaging side of 2.5D design, more needs to be resolved when it comes to improving yields. Proponents of 2.5D present compelling benefits. Arif Rahman, a product architect at Altera, noted that the industry trend of silicon convergence is leading to multiple technologies being integrated into single-chip solutions. “2.5D/3D integration has multiple adva... » read more

Getting A Clearer Picture
By Geir Eide - 17 Apr, 2014 - Comments: 1

Scan test diagnosis is an established software-based methodology for localizing defects causing failures in digital semiconductor devices. Using structural test patterns (such as ATPG) and the design description, diagnosis turns failing test cycles into valuable data. Exactly how valuable this data is depends on the quality of the diagnosis results. A result that points to a small group of nets... » read more

Effectively Manage Material Obsolescence To Avoid Costly Surprises
By Various Writers - 16 Apr, 2014 - Comments: 0

This paper describes the solution that allows complete management and control for companies to optimize their business and their performance on commitment to customers, specifically with respect to effective management of material obsolescence. To view this paper, click here. » read more

Blog Review: April 16
By Ed Sperling - 16 Apr, 2014 - Comments: 0

Cadence’s Richard Goering attended a workshop on “extreme” scale design automation, which looked at where else EDA tools can be used—such as intelligent traffic lights. At least there are well-defined use cases. Mentor’s Nazita Saye has compiled five predictions from the 1964 New York World’s Fair that are worth revisiting. Three of them came true. Check out the ones that didn’... » read more

A Guide To Advanced Process Design Kits
By Ernest Worthman - 14 Apr, 2014 - Comments: 1

The increasing complexity of design enablement has prompted manufacturers to optimize the design process. New tools and techniques, thanks to next-generation hardware and software, have provided a new platform for semiconductor and wafer design. Advanced PDKs are the solution and have been developed by foundries to optimize the design process and leverage and reuse intellectual property (IP) an... » read more

Favorite Forecast Fallacies
By Barry Pangrle - 14 Apr, 2014 - Comments: 0

It’s difficult to make predictions, especially about the future. – An Old Danish Proverb. The GSA Silicon Summit was held on Thursday, April 10th at the Computer History Museum in Mountain View, CA. The opening panel session was entitled Advancements in Nanoscale Processing. The panelists were Rob Aitken (ARM), Adam Brand (Applied Materials), Peter Huang (TSMC), Nick Kepler (VLSI Researc... » read more

The Week In Review: Design
By Ann Mutschler - 11 Apr, 2014 - Comments: 0

Tools Mentor Graphics announced its Enterprise Verification Platform (EVP) that pulls together the company’s Questa verification technologies with Veloce OS3 global emulation resourcing technology, and the Visualizer debug technology into what it says is a globally accessible, high-performance datacenter resource. The system is aimed at global resource management and supports project teams a... » read more

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