tag: Moore’s Law

Focus Shifts To Architectures
By Ed Sperling - 08 Sep, 2016 - Comments: 1

Chipmakers increasingly are relying on architectural and micro-architectural changes as the best hope for improving power and performance across a spectrum of markets, process nodes and price points. While discussion about the death of [getkc id="74" comment="Moore's Law"] predates the 1-micron process node, there is no question that it is getting harder for even the largest chipmakers to st... » read more

All You Need Is Cache (Coherency) To Scale Next-Gen SoC Performance
By Kurt Shuler - 25 Aug, 2016 - Comments: 0

Life on the SoC performance front remains a withering battle sometimes, because things can seem fairly bleak. As transistor scaling becomes more expensive below 10-nanometer feature sizes, every day it becomes harder to double performance every 18-months or so and stay competitive. Nowhere is the pain of this battle more acute than in consumer and automotive systems, where low cost is the key t... » read more

Deeper Inside Intel
By Mark LaPedus - 22 Aug, 2016 - Comments: 5

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

How Small Will Transistors Go?
By Mark LaPedus - 18 Aug, 2016 - Comments: 1

By Mark LaPedus & Ed Sperling There is nearly universal agreement that Moore’s Law is slowing down. But whether it will truly end, or just become too expensive and less relevant—and what will supplant device scaling—are the subject of some far-reaching research and much discussion. Semiconductor Engineering sat down with each of the leaders of three top research houses—[getent... » read more

Mask Maker Worries Grow
By Mark LaPedus - 18 Aug, 2016 - Comments: 2

Leading-edge photomask makers face a multitude of challenges as they migrate from the 14nm node and beyond. Mask making is becoming more challenging and expensive at each node on at least two fronts. On one front, mask makers must continue to invest in the development of traditional optical masks at advanced nodes. On another front, several photomask vendors are preparing for the possible ra... » read more

How To Achieve Faster Design Convergence And A Better Design
By Muhammad Zakir - 15 Aug, 2016 - Comments: 0

We find ourselves at an interesting point in the evolution of semiconductor technologies electronic systems as a whole. As Moore’s Law continues to charge forward, tools and workflows continue to adapt to major trends, including: Increasing system design complexity; The increasing digital footprint of both design databases and simulation output data, and New architectures/More-than-Mo... » read more

New Drivers For Test
By Brian Bailey - 28 Jul, 2016 - Comments: 0

Mention Design for Test (DFT) and scan chains come to mind, but there is much more to it than that—and the rules of the game are changing. New application areas such as automotive may breathe new life into built-in self-test (BIST) solutions, which could also be used for manufacturing test. So could DFT as we know it be a thing of the past? Or will it continue to have a role to play? Te... » read more

Material And Process Challenges In A Changing Memory Landscape
By Er-Xuan Ping - 21 Jul, 2016 - Comments: 0

Moore’s Law has fueled the semiconductor industry’s growth for decades. But as the complexity of scaling increases, extending the economics of Moore’s Law is becoming a challenge. One example illustrating the challenges of maintaining the economic benefits of Moore’s Law is the difficulty of IC chip patterning. Today, this requires an expensive litho scanner, a complicated spacer and... » read more

To 7nm And Beyond
By Ed Sperling - 21 Jul, 2016 - Comments: 4

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], and Thomas Caulfield, senior vice president and general manager of Fab 8, sat down with Semiconductor Engineering to discuss future directions in technology, including the next rev of FD-SOI, the future of Moore’s Law, and how some very public challenges will likely unfold. SE: What do you see as the... » read more

Building Faster Chips
By Ed Sperling - 21 Jul, 2016 - Comments: 5

By Ed Sperling and Jeff Dorsch An explosion in IoT sensor data, the onset of deep learning and AI, and the commercial rollout of augmented and virtual reality are driving a renewed interest in performance as the key metric for semiconductor design. Throughout the past decade in which mobility/smartphone dominated chip design, power replaced performance as the top driver. Processors ha... » read more

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