tag: power integrity

Clocked DDR5 Client Memory Modules Enable Scaling To 9600 MT/s For AI PCs
By Carlos Weissenberg - 11 Jun, 2026 - Comments: 0

AI PCs are driving a new class of client workloads that behave very differently from traditional productivity or multimedia applications. Agentic AI systems are expected to plan, execute, and adapt in real time, maintaining persistent context while orchestrating multiple concurrent tasks. These usage patterns place sustained pressure on the memory subsystem, requiring not only higher peak bandw... » read more

Powering AI At Scale: Why 3D-ICs Demand A New Approach To Power Integrity
By Muhammad Hassan - 07 May, 2026 - Comments: 0

By Muhammad Hassan and Sudarshan Deo The semiconductor industry is undergoing a fundamental transition. Performance scaling is no longer driven primarily by transistor density, but by advanced packaging—2.5D, 3D-ICs, chiplets, and heterogeneous integration. Fig. 1: 3D-IC and 2.5D structure. These architectures are essential to meeting the extreme performance and bandwidth demands... » read more

Power Integrity Without Blind Spots: A System Level Approach To 3D-ICs
By Muhammad Hassan - 09 Apr, 2026 - Comments: 0

Power delivery has become one of the defining challenges of next-generation semiconductor systems. As AI, high-performance computing, and data-centric workloads drive higher performance and tighter integration, traditional 2D SoC design approaches are reaching their limits. The industry’s shift toward 2.5D and 3D heterogeneous integration promises breakthroughs in performance and efficiency�... » read more

Noise: A Chip Killer
By Brian Bailey - 13 Nov, 2025 - Comments: 0

Noise has always been important to communications experts, but it's quickly becoming an issue that every semiconductor designer has to contend with. Some chips already have been compromised. Noise can be defined as any deviation from the ideal that can impact intended functionality. When it comes to semiconductors, that could mean the ability to reliably extract a signal value at the intende... » read more

Power Integrity And Voltage Issues Get Harder To Detect And Solve
By Ann Mutschler - 13 Nov, 2025 - Comments: 0

Voltage and power integrity are becoming increasingly critical and challenging for chip designers and architects, regardless of which process technology they are using or which market they are targeting. An explosion of features vying unevenly for current is increasing the number of constraints and possible interactions that engineers need to sort through to ensure reliability. These include... » read more

A Signal Integrity Guide to HSD PCB Design
By Cadence - 27 Aug, 2025 - Comments: 0

As data rates soar into the multi-gigabit range, high-speed digital (HSD) PCB design is no longer just about connecting the dots. Signal integrity (SI) and power integrity (PI) challenges can silently destroy performance—long before your board even hits the lab. This comprehensive guide is your blueprint for mastering SI fundamentals in complex, high-speed PCB systems. From PCIe and DDR t... » read more

What Is Electronic Design Automation And Why Do You Need It?
By Roberto Piacentini Filho - 24 Apr, 2025 - Comments: 0

As data speeds push into the multi-gigabit range and requirements on digital systems grow more complex, cutting down the time-to-market while also ensuring error-free reliable designs seems impossible. Traditional design tools and practices can result in failed prototypes, costly respins, delayed time-to-market, missed market opportunities, and subpar performance. This is why advanced EDA to... » read more

Accelerating SI/PI Signoff: A Shift-Left Approach to PCB Design
By Cadence - 23 Apr, 2025 - Comments: 0

In high-speed PCB design, late-stage signal integrity (SI) and power integrity (PI) issues can lead to costly redesigns and delays. This white paper explores how in-design analysis helps engineers catch and fix SI/PI challenges early, saving time, reducing risks, and ensuring first-pass success. What You’ll Learn: The Shift-Left Advantage – How early SI/PI analysis minimizes late-s... » read more

Co-Design Optimization For PI/SI When Considering Thermal Performance
By Peater Wu - 21 Apr, 2025 - Comments: 0

When applications become more complex, higher data rates or high frequencies are required. However, with increasing functions, more power dissipation will be generated. Furthermore, temperature is proportional to power dissipation, so electrical performance will also depend on thermal conditions. To determine how temperature impacts power integrity/signal integrity (PI/SI), electrical simulatio... » read more

Chiplets Add New Power Issues
By Ann Mutschler - 13 Mar, 2025 - Comments: 0

Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors. Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors... » read more

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