tag: Real Intent

Start Verification Early To Avoid Pitfalls Later
By Ann Mutschler - 24 Oct, 2013 - Comments: 1

It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made. Harry Foster, chief scientist for v... » read more

Trending Back To ASICs
By Ann Mutschler - 24 Oct, 2013 - Comments: 0

True to its cyclical nature, the semiconductor industry is swinging back toward ASICs from more diversified approaches such as FPGAs. This dynamic is evident at companies such as Apple. “At one point we thought Apple was being a contrarian,” said Drew Wingard, CTO at Sonics. “Everybody else on the systems side was shedding their silicon people. The easiest counterpoint to what Apple wa... » read more

A Night to Remember: EDA Back to the Future
By Graham Bell - 24 Oct, 2013 - Comments: 0

I had the pleasure to attend the EDA: Back to the Future event at the Computer History Museum on Oct. 16.   There were over 230 guests to raise money for the EDA Oral History Project at the Museum.   There were industry luminaries honored at the event, and I did red carpet interviews with many of them as they arrived including Joe Costello, Simon Segars, and Penny Herscher.  As I did the i... » read more

CDC Methodology For Fast-To-Slow Clocks
By Various Writers - 24 Oct, 2013 - Comments: 0

CDC checking of any asynchronous clock domain crossing requires that the data path and the control path be identified and that the receive clock domain data flow is controlled by a multiplexer with a select line that is fed by a correctly synchronized control line.  Meridian CDC identifies all the data and associated control paths in a design and will ensure that the control signals passing fr... » read more

Blog Review: Oct. 16
By Ed Sperling - 16 Oct, 2013 - Comments: 0

Cadence’s Richard Goering follows Si2’s move into SPICE modeling following the acquisition of the Compact Model Council. Combining standards groups is a growing trend these days. Mentor’s Colin Walls points to the demise of reset buttons. You can always trip a circuit breaker, and usually turn off a device by pulling out the battery, but a reset button is simpler. Where did they go? ... » read more

Blog Review: Oct. 9
By Ed Sperling - 09 Oct, 2013 - Comments: 0

By Ed Sperling Mentor’s Simon Favre raises an interesting question: Why are 450mm wafers and EUV lithography related? The answer may surprise you. In his second broadcast, Cadence’s Brian Fuller interviews Gary Smith about where EDA will grow, why industry consolidation is a myth and why there is a dearth of reliable information about the electronics industry. Synopsys’ Mick Posner... » read more

Executive Briefing: Prakash Narain
By Ed Sperling - 12 Jul, 2013 - Comments: 0

Real Intent CEO Prakash Narain talks with System-Level Design about where are the pain points in verification; different types of signoff; the impact of third-party IP, and can the tools industry keep up with the rising complexity in semiconductor design. [youtube vid=C25VMRDXGAQ] » read more

The New Verification Landscape
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler Verification technologies and tools have never been more sophisticated. But putting together a methodology is more than just putting tools together. It starts with trying to get a handle on the complexity, knowing what to test, how to test and when. “UVM was standardized and people have been working to adopt that which has been generally a positive,” said Steve Ba... » read more

Best-In-Class Tools Lead To Best-In-Class Design?
By Graham Bell - 27 Jun, 2013 - Comments: 0

Today’s systems on chip (SoC) are deeply complex in new ways. A dozen or so years ago, a state-of-the-art processor such as the Intel Pentium 4 used 42 million transistors, was built on a 180nm process and relied upon discrete chips to handle its system interfaces. Jump forward, and the Intel Xeon Phi processor that Intel introduced in 2012 uses 5 billion transistors and is built on a 22nm pr... » read more

The Week In Review: June 21
By Ed Sperling - 21 Jun, 2013 - Comments: 0

By Ed Sperling Mentor Graphics rolled out emulation-ready verification IP for MIPI camera and display-based protocols. The VIP enables stimuli generated by UVM and SystemC-based environments and applies them to a design under test (DUT) running in the emulator. Synopsys introduced a tool for implementing and verifying functional engineering change orders, including matching, visualization ... » read more

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