Re-Architecting SerDes


Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Low Power Still Leads, But Energy Emerges As Future Focus


In 2021 and beyond, chips used in smartphones, digital appliances, and nearly all major applications will need to go on a diet. As the amount of data being generated continues to swell, more processors are being added everywhere to sift through that data to determine what's useful, what isn't, and how to distribute it. All of that uses power, and not all of it is being done as efficiently as... » read more

Waking And Sleeping Create Current Transients


Silicon power-saving techniques are helping to reduce the power required by data centers and other high-intensity computing environments, but they’ve also added a significant challenge for design teams. As islands on high-powered chips go to sleep and wake up, the current requirements change quickly. This happens in a few microseconds, at most. The rapid change of loading creates a challen... » read more

Detecting Electrical Hazards Incurred By Inter-Voltage Domain Crossing In Custom SRAMs


Fast-growing markets, such as 5G, biotechnology, AI, and automotive, are driving a new wave of low-power semiconductor design requirements and, hence, more aggressive low-power management techniques are needed. Consequently, even large macros within a chip, such as SRAMs, now feature multiple voltage domains to limit power draw during light-sleep, deep-sleep, and shutdown-low-power modes. These... » read more

Blog Review: Dec. 9


Arm's Benoit Labbe digs into designing a power converter for Arm Research's ultra-low power M0N0 microcontroller, with a focus on optimal efficiency and leakage constraints. Mentor's Harry Foster tries to get a sense of how much effort is spent in verification of FPGAs by looking at the amount of time spent and number of engineers on a project. Cadence's Paul McLellan listens in as Odile ... » read more

Digital Test Bulks Up – Or Down


Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

Completing The Silicon Lifecycle Management Puzzle


The year 2020 will be remembered for many reasons. The global pandemic, the political struggles and the extreme weather will occupy our thoughts for many years. There was another event that occurred in 2020 that will also be remembered in a smaller, but very important portion of the world. It’s the year that Synopsys acquired Moortec to complete the silicon lifecycle management (SLM) puzzle. ... » read more

Infrastructure Impacts Data Analytics


Semiconductor data analytics relies upon timely, error-free data from the manufacturing processes, but the IT infrastructure investment and engineering effort needed to deliver that data is, expensive, enormous, and still growing. The volume of data has ballooned at all points of data generation as equipment makers add more sensors into their tools, and as monitors are embedded into the chip... » read more

IP Safe Enough To Use In Cars


IP that is used for functional safety needs to respond to events that can happen, whether those are planned or random. Jody Defazio, vice president of IP quality and functional safety at Synopsys, talks with Semiconductor Engineering about ASIL compliance, what the different levels mean, and the impact of using chips developed at the most advanced process nodes in automotive applications. » read more

Change Management With Impact Analysis During Safety-Critical IP And SoC Development


Standards like ISO 26262 provide guidance to mitigate safety risks by defining safety analyses requirements and processes. The standard describes Change Management as a way to analyze and control changes in safety-related work products, items, and elements throughout the safety lifecycle. Impact analysis, a part of the Change Management process, is a systematic approach for evaluating changes t... » read more

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