tag: Synopsys

Blog Review: April 5
By Jesse Allen - 05 Apr, 2017 - Comments: 0

In a video, Cadence's Megha Daga digs into the different architectural layers present in convolutional neural networks and how they contribute to object detection and classification in a real world scenario. Mentor's Mike Santarini argues that as things become increasingly connected, the stakes of bad design and bad verification are higher than they've ever been. Synopsys' Robert Vamosi w... » read more

The Great Machine Learning Race
By Ed Sperling - 03 Apr, 2017 - Comments: 2

Processor makers, tools vendors, and packaging houses are racing to position themselves for a role in machine learning, despite the fact that no one is quite sure which architecture is best for this technology or what ultimately will be successful. Rather than dampen investments, the uncertainty is fueling a frenzy. Money is pouring in from all sides. According to a new Moor Insights report,... » read more

The Week In Review: Design
By Jesse Allen - 31 Mar, 2017 - Comments: 0

M&A Siemens closed the acquisition of Mentor Graphics, making Mentor now part of Siemens' product lifecycle management (PLM) software business. The $4.5 billion deal, announced last November, brings Siemens into the IC design tool and embedded software markets and expands Siemens' multi-physics and electronic simulation capabilities in the growing digital twin space, which ties together ... » read more

HBM Upstages DDR In Bandwidth, Power
By Ann Mutschler - 30 Mar, 2017 - Comments: 1

For graphics, networking, and high performance computing, the latest iteration of high-bandwidth memory (HBM) continues to rise up as a viable contender against conventional DDR, GDDR designs, and other advanced memory architectures such as the Hybrid Memory Cube. [getkc id="276" kc_name="HBM"] enables lower power consumption per I/O and higher bandwidth memory access with a more condensed f... » read more

Learn From The Experts
By Tom De Schutter - 29 Mar, 2017 - Comments: 0

I visited SNUG Silicon Valley last week. This annual Synopsys User Group event at the Santa Clara Convention Center is always a good way to get in touch with the end users of various EDA products. I attended the technical track with experts from ARM, NVIDIA, Intel and Synopsys, who talked about their experience in accelerating software development, hardware verification and system validation... » read more

Custom Chip Verification Issues Grow
By Ann Mutschler - 29 Mar, 2017 - Comments: 0

With the transition to finFETs, design conditions have grown more intense. They now include a wider PVT range and less headroom. As a result, electronic systems for applications such as mobile, consumer, and automotive increasingly are becoming more difficult to design due to the exacting performance requirements of these applications. This is particularly evident in custom design, including... » read more

Blog Review: March 29
By Jesse Allen - 29 Mar, 2017 - Comments: 0

In a video, Cadence's Megha Daga introduces how convolutional neural networks identify objects and the wide range of applications for the technology. Mentor's Ron Press proposes a way to take advantage of hierarchical DFT features, even if a design wasn't designed for it. Synopsys' Robert Vamosi shares highlights of the RAND Corporation's extensive report examining zero day vulnerabilitie... » read more

The Week In Review: Design
By Jesse Allen - 24 Mar, 2017 - Comments: 0

Tools Synopsys revealed a comprehensive low power reference kit for design and verification based on a bitcoin mining SoC design. The kit is designed to help accelerate deployment of a Unified Power Format (UPF)-based hierarchical design methodology and as a learning vehicle for the complete Synopsys low power flow. Space Codesign introduced the latest version of its simulation environmen... » read more

Challenges Grow For IP Reuse
By Ann Mutschler - 23 Mar, 2017 - Comments: 3

As chip complexity increases, so does the complexity of IP blocks being developed for those designs. That is making it much more difficult to re-use IP from one design to the next, or even to integrate new IP into an SoC. What is changing is the perception that standard [getkc id="43" kc_name="IP"] works the same in every design. Moreover, well-developed [getkc id="100" kc_name="methodologie... » read more

The CEO Outlook Returns
By Bob Smith - 23 Mar, 2017 - Comments: 0

One of the more popular events hosted by the EDA Consortium (EDAC, to those in the know) was the CEO Forecast held at the start of each year. It was phased out several years ago for a number of reasons, including logistics and scheduling. Attendance was never one of them. As I took the reins of EDAC two years ago, I repeatedly heard how much that evening was missed. Members and non-members h... » read more

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